Design Validation & Test (DVT) Engineer (multiple roles/openings)

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer in Irvine, CA to spearhead post-silicon validation for next-generation coherent DSP ASICs enabling AI and hyperscale networking.

You will drive silicon characterization, enable first silicon bring-up, and build validation infrastructure while collaborating across Architecture, RTL, Firmware, Systems, and Customer Engineering. Strong leadership and a strategic validation mindset are required.

Qualifications

• 8+ years in post-silicon validation, DVT, or silicon bring-up with complex ASICs/SoCs.
• Experience bringing first silicon to production in networking, data center, AI, or HPC products.
• Strong understanding of silicon debug methodologies and root-cause analysis.
• Proficient in Python for automation, regression, and data analysis.
• Experience validating firmware, embedded software, drivers, and HW/SW interfaces.

Responsibilities

• Lead post-silicon validation and characterization from first silicon through production release.
• Develop validation plans for functionality, performance, interoperability, stress, and reliability.
• Enable first silicon bring-up using JTAG, scan, and embedded debug features.
• Validate high-speed interfaces like PCIe, Ethernet, SerDes, CXL, SPI, I2C, MDIO.
• Develop automation frameworks for test execution, regression, and data analysis.
• Document validation results and production readiness reports.

Skills

Post-silicon validation

Python automation

Root-cause analysis

Hardware debugging

Cross-functional collaboration

Communication skills

On-site work readiness

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Oscilloscopes

BERTs

Protocol analyzers

Logic analyzers

Network analyzers

Power measurement equipment

Job description

• Irvine, CA

Junior / Senior / Principal Design Validation & Test (DVT) Engineer roles

Irvine, CA

About The Role

Celero is seeking an experienced Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking. As a key member of our engineering team, you will play a critical role in enabling first silicon, driving silicon characterization, and ensuring product readiness for customer deployment and high-volume production.

This is a highly visible technical leadership role within a fast-paced startup where you will work closely with Architecture, RTL Design, Firmware, Systems, Product Engineering, and customers to solve complex silicon challenges. You will have the opportunity to influence validation strategy, define best practices, and help build our validation infrastructure from the ground up.

What You'll Do

• Lead post-silicon validation and characterization of complex ASICs and SoCs from first silicon through production release.


• Develop comprehensive validation plans covering functionality, performance, interoperability, compliance, stress testing, corner cases, and reliability.


• Enable first silicon bring-up using JTAG, scan, embedded debug features, and board-level diagnostics.


• Validate high-speed interfaces including PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, and other industry-standard protocols.


• Utilize advanced lab equipment including high-bandwidth oscilloscopes, BERTs, protocol analyzers, Ethernet traffic generators, network analyzers, logic analyzers, and power measurement equipment.


• Debug complex hardware, firmware, RTL, and system-level issues while working closely with cross-functional engineering teams to identify root cause and drive timely resolution.


• Develop scalable Python-based automation frameworks for test execution, regression, silicon characterization, data analysis, and reporting.


• Validate firmware, bootloaders, device drivers, and hardware/software interfaces across multiple platforms.


• Characterize silicon performance, power, thermal behavior, margins, and compliance against architectural specifications.


• Lead debug reviews and provide technical direction for validation methodology, infrastructure, and best practices.


• Support early customer engagements by reproducing and resolving system-level issues and collaborating with applications engineering.


• Document validation results, silicon characterization data, debug findings, and production readiness reports.

What You'll Bring

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.


• 8+ years of hands-on post-silicon validation, DVT, or silicon bring-up experience with complex ASICs or SoCs.


• Proven experience bringing first silicon to production in networking, communications, data center, AI, or high-performance computing products.


• Strong understanding of silicon debug methodologies and structured root-cause analysis.


• Extensive experience using laboratory equipment including oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, and related validation tools.


• Strong knowledge of one or more high-speed protocols including PCIe, Ethernet, SerDes, CXL, USB, SPI, I²C, or similar interfaces.


• Strong Python programming skills for automation, regression development, and data analysis.


• Experience validating firmware, embedded software, drivers, and hardware/software interfaces.


• Ability to interpret schematics, understand board design, power sequencing, signal integrity, and hardware debug.


• Excellent communication skills with the ability to work effectively across Architecture, Design, Firmware, Systems, Product Engineering, Manufacturing, and Customer Engineering teams.


• Comfortable working in a fast-paced startup environment where priorities evolve quickly and every team member has significant technical ownership.


• Ability to work onsite at our Irvine, California headquarters.

Preferred Qualifications

• Experience validating coherent optical DSPs, networking ASICs, Ethernet switch silicon, AI accelerators, GPUs, storage controllers, or high-speed communications devices.


• Strong knowledge of Ethernet, PCIe, OIF, IEEE, or related compliance specifications.


• Experience with PIPE, PCS, PMA, MAC, PHY, or other physical and protocol layers of high-speed interfaces.


• Experience building scalable validation automation, regression systems, dashboards, and data pipelines.


• Familiarity with customer platform validation and hyperscale qualification processes.


• Experience mentoring engineers and leading technical initiatives across multiple engineering disciplines.

Why Celero

At Celero, you'll help develop the next generation of coherent DSP technology enabling AI infrastructure and hyperscale networking. As a Principal Engineer, you'll have the opportunity to influence product architecture, shape validation strategy, work alongside industry leaders, and make a significant impact within a collaborative, high-growth startup environment where innovation, ownership, and technical excellence are valued every day

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)