Principal Physical Verification Engineer

Celero Communications; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Full-Chip Physical Verification Engineer to own all aspects of PV execution on advanced nodes.

You will lead full-chip and block PV checks, drive schedules, and ensure tapeout readiness while collaborating with Analog and Physical Design teams to meet performance and manufacturability targets. The role requires a 7+ year track record in full-chip PV, experience with ICV/Calibre, and scripting skills in Python/Tcl.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications.

Responsibilities

• Lead full chip Physical Verification effort.
• Own execution plans and schedules for full-chip PV.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks.
• Own the full chip verification scope.
• Collaborate with analog team to ensure clean IP delivery.
• Run and analyze DRC/ERC/LUP/PERC results.
• Use ICV or Calibre verification tools.
• Understand advanced TSMC DRC rules.
• Partner with analog/block/chip top owners for clean floorplan.
• Provide guidance on corner-case requirements.
• Influence floorplan constraints, hierarchy and implementation strategy.
• Participate in tapeout readiness reviews.

Skills

Full-chip PV

Team leadership

PV execution planning

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

ICV

Calibre

Python

Tcl

Shell scripting

Job description

Celero Communications, Inc. is an exciting and fast-growing semiconductor startup developing high-performance coherent digital signal processors (DSPs) for optical interconnects used in large-scale AI infrastructure. Celero's goal is to enable higher-bandwidth, lower-power optical connectivity between AI clusters and data centers.

We are seeking a Full-Chip Physical Verification Engineer to join our Physical Design team and help deliver complex digital blocks and full-chip implementations in advanced process technologies. This role will own all aspects of Physical Verification execution on advanced TSMC nodes, ensuring design quality, manufacturability, and tapeout readiness. The ideal candidate has successfully completed multiple tapeouts and brings deep expertise in physical verification methodologies, including driving improvements in quality, execution efficiency, and predictable delivery across multiple programs. You will work closely with the Analog Design and Physical Design teams to identify and resolve verification challenges while ensuring designs meet aggressive performance, manufacturability, and schedule objectives.

Locations

San Jose, CA (preferred) or Irvine, CA (HQ)

Key Responsibilities

Team & Project Leadership

• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks

Physical Verification Ownership

• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules

Cross-Functional Collaboration

• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications

Proven Hands-on Experience With

• Physical Verification tool (ICV/Calibre)
• Able to assemble a flow to support block/chip level PV

Strong Expertise In

• Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration

Preferred Qualifications

• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)