Lead Physical Design Engineer: PnR, PPA & Timing Closure

Vaspire Technologies Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Vaspire Technologies Inc. is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence expertise for advanced nodes.

You will drive block-level implementation from netlist to GDSII, perform floorplanning, placement, CTS, routing, and verification, and collaborate with RTL/DFT teams to ensure successful tapeout. You will optimize for power, performance, and area, develop timing constraints, and address EMIR and signoff challenges across multiple corners.

Qualifications

• Experience in physical design and PnR for advanced nodes.
• Proficient in floorplanning, CTS, routing, and timing closure.
• Familiar with signoff methodologies and EDA tools.

Responsibilities

• Drive block-level physical design from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and verification.
• Optimize designs for PPA targets (Power, Performance, Area).
• Achieve timing closure across corners and modes.
• Analyze and resolve setup/hold/transition violations and noise.
• Develop timing constraints (SDC) and STA signoff methodologies.
• Conduct EMIR analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams for tapeout.
• Debug physical design issues and drive convergence within schedules.

Skills

Physical Design

PnR flow

Floorplanning

Placement & Optimization

CTS

Routing

Timing Closure

STA

SDC

EMIR Analysis

PPA Optimization

EDA Tools

Cadence Innovus

RedHawk/Voltus

Low-Power Design

Education

Electrical Engineering degree

Tools

Cadence Innovus

RedHawk

Voltus

Job description

Vaspire Technologies Inc. is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence expertise for advanced nodes.

You will drive block-level implementation from netlist to GDSII, perform floorplanning, placement, CTS, routing, and verification, and collaborate with RTL/DFT teams to ensure successful tapeout. You will optimize for power, performance, and area, develop timing constraints, and address EMIR and signoff challenges across multiple corners.