Physical Design Engineer

Globex Digital Corp.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Globex Digital Corp. seeks a Physical Design Engineer for Austin, TX to lead PnR/VLSI flow, floorplanning, CTS, routing, and timing convergence. You will optimize Power-Performance-Area (PPA) and ensure timing closure across multiple corners while addressing SETUP/HOLD violations and EMIR concerns.

You will collaborate with RTL, DFT, STA, and Signoff teams to drive tapeout readiness and design convergence within project schedules.

Qualifications

• Experience with physical design flows from netlist to GDSII.
• Proven ability to achieve timing closure across corners.
• Knowledge of EMIR analysis and IR drop.
• Experience with low-power design techniques.
• Strong debugging and cross-functional collaboration.

Responsibilities

• Drive block-level physical design from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and signoff.
• Develop timing constraints (SDC) and STA methodologies.
• Collaborate with RTL, DFT, and Signoff teams.
• Debug physical design issues to meet tapeout schedules.

Skills

Physical Design

PnR flow

Floorplanning

Placement & Optimization

CTS

Routing

Timing Closure

STA

SDC

EMIR Analysis

PPA Optimization

EDA Tools

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Cadence Innovus

RedHawk/Voltus

Job description

Role: Physical Design Engineer (PnR / PPA / Timing Closure)

Location: Austin, TX

Job Description

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Key Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Required Skills

• Strong experience in Physical Design and PnR flow.
• Floorplanning
• Placement & Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• Static Timing Analysis (STA)
• Timing Constraints (SDC)
• EMIR Analysis
• PPA Optimization
• Experience with industry-standard EDA tools such as:
  • Cadence Innovus (optional)
  • RedHawk / Voltus (EMIR)
• Good understanding of low-power design techniques and signoff methodologies.

Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.