Lead Physical Design Engineer, AI Accelerator Platform

Acceler8 Talent; Mountain View (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Acceler8 Talent is seeking a senior physical-design engineer to own blocks of a next‑gen AI accelerator from floorplanning through sign‑off. You will drive timing, power, area, and verification requirements with architects and RTL teams, while coordinating with foundries, EDA vendors and packaging partners to ensure timely tape-out.

The role targets 7nm or below with hands‑on experience in full-flow PD, using Cadence Innovus, Fusion Compiler, and PrimeTime/Tempus for sign-off.

Qualifications

• 8+ years of hands-on physical-design experience.
• Experience with high-performance designs at 7nm or below.
• Full-flow ownership from synthesis and floorplanning through sign-off.
• Hands-on timing sign-off experience using PrimeTime, Tempus, or equivalent.
• Experience working closely with architecture, RTL, foundry, and EDA teams.
• Track record of taking complex silicon through tape-out.

Responsibilities

• Own physical design for one or more blocks of a new AI accelerator from floorplanning through sign-off.
• Close timing, power, area, congestion, and physical-verification requirements.
• Develop AI-assisted flows to accelerate physical-design and sign-off timelines.
• Collaborate with architects and RTL designers to resolve implementation trade-offs.
• Work with EDA vendors, foundries, packaging, and verification teams.
• Deliver complex blocks through tape-out and first silicon.

Skills

Physical design

Floorplanning

Synthesis

Placement

Routing

Timing closure

Power/area/congestion

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

Acceler8 Talent is seeking a senior physical-design engineer to own blocks of a next‑gen AI accelerator from floorplanning through sign‑off. You will drive timing, power, area, and verification requirements with architects and RTL teams, while coordinating with foundries, EDA vendors and packaging partners to ensure timely tape-out.

The role targets 7nm or below with hands‑on experience in full-flow PD, using Cadence Innovus, Fusion Compiler, and PrimeTime/Tempus for sign-off.