Lead Physical Design Engineer - AI Accelerator SoC

Acceler8 Talent; Mountain View (CA); On-site; USD 210,000 - 280,000; Full time

Benefits offered by this job

Equity participation

Medical coverage

Dental coverage

Vision coverage

401(k)

Paid time off

Job summary

Acceler8 Talent seeks a Principal Physical Design Engineer to own the complete physical implementation of critical blocks within a high-performance AI accelerator SoC, from floorplanning to tapeout. You will work with architects, RTL, verification, and software teams to deliver first-generation silicon and lay the foundation for future generations.

The role demands 8+ years of experience in physical design for complex ASICs at advanced nodes, with hands-on use of Cadence Innovus, Synopsys Fusion

Qualifications

• 8+ years of physical design experience for complex ASICs at advanced nodes (7nm or below).
• Full implementation flow expertise: synthesis, place & route, CTS, timing closure, phy verifications, signoff.
• Proven use of Cadence Innovus, Fusion Compiler, and signoff tools like PrimeTime/Tempus.

Responsibilities

• Own the complete physical design flow for one or more SoC blocks from floorplanning to signoff.
• Develop AI-assisted implementation methodologies to boost productivity and tapeout speed.
• Drive P&R, CTS, timing closure, power optimization, and physical verification.
• Collaborate with architecture, RTL, verification, and software to optimize performance, power, and area.
• Partner with EDA vendors and foundries to resolve issues and deliver production-ready silicon.

Skills

Physical design

Floorplanning

Synthesis & P&R

Timing closure

Power optimization

Cross-functional collaboration

7nm node experience

EDA teamwork

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

Acceler8 Talent seeks a Principal Physical Design Engineer to own the complete physical implementation of critical blocks within a high-performance AI accelerator SoC, from floorplanning to tapeout. You will work with architects, RTL, verification, and software teams to deliver first-generation silicon and lay the foundation for future generations.

The role demands 8+ years of experience in physical design for complex ASICs at advanced nodes, with hands-on use of Cadence Innovus, Synopsys Fusion