Lead Memory Subsystem Architect & ASIC RTL Engineer

Oho Group; San Francisco (CA); On-site; USD 250,000 - 450,000; Full time

Job summary

Oho Group is seeking a lead-level engineer to own a memory subsystem, spanning architecture, RTL design and silicon implementation.

This hands-on role challenges you to solve complex hardware problems across multiple areas of chip development, while providing technical guidance and mentoring to other engineers.

Strong candidates will have 15+ years of memory controller experience and a proven ability to deliver high-performance ASIC designs through the full development lifecycle.

Qualifications

• 15+ years of experience in memory controller or memory subsystem design.
• Hands-on ASIC/SoC RTL development experience.
• Deep understanding of memory architecture and controller design.
• Experience with DRAM or high-performance memory technologies.
• Experience delivering designs through the ASIC development lifecycle.
• Strong trade-off awareness for performance, power, and area.

Responsibilities

• Own memory subsystem architecture and microarchitecture through implementation.
• Design and develop high-performance memory controller logic.
• Write and review SystemVerilog RTL.
• Optimise designs for performance, power and area.
• Collaborate with verification and physical design teams to meet goals.
• Contribute to timing, synthesis, CDC and design-quality activities.
• Help debug complex hardware issues throughout the development cycle.
• Provide technical guidance and mentorship to other engineers.

Skills

Memory subsystem design

ASIC/SoC RTL development

Memory architecture

DRAM/memory tech

Cross-functional leadership

Ownership & mentoring

Tools

SystemVerilog

RTL development tools

EDA tools

Job description

Oho Group is seeking a lead-level engineer to own a memory subsystem, spanning architecture, RTL design and silicon implementation.

This hands-on role challenges you to solve complex hardware problems across multiple areas of chip development, while providing technical guidance and mentoring to other engineers.

Strong candidates will have 15+ years of memory controller experience and a proven ability to deliver high-performance ASIC designs through the full development lifecycle.