Lead Logic Design Engineer — Hybrid (Memory IP)

Rambus; Hillsboro (OR); Híbrido; USD 150 000 - 230 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Hybrid work model

Equity and bonus package

Resumo da oferta

Rambus, a premier chip and silicon IP provider, seeks a Lead Member of Technical Staff (LMTS) – Logic Design to join our Silicon IP team in Hillsboro, Oregon. You will contribute to micro-architecture and RTL design for high-performance memory controllers for data centers and AI applications.

This role is an individual contributor reporting to the Director of Engineering, with a hybrid work model that includes on-site collaboration and some remote work.

Qualificações

• Strong SystemVerilog/Verilog RTL design expertise.
• Questa/Incisive/VCS simulator experience.
• Python/Perl/TCL scripting experience.
• Ability to learn quickly and work independently.
• Solid communication and project management skills.
• 8+ years of logic design experience (ASIC/FPGA) with BS EE, or 6+ years with MS EE.

Responsabilidades

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces.
• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data.
• Collaborate closely with verification team to shape test plans and improve verification coverage.
• Work with physical design team to understand and resolve timing, power, and congestion challenges.
• Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary.
• Provide technical support to FAE team on pre-sales customer engagements.
• Provide technical support to AE team on post-sale s customer deliveries.

Conhecimentos

SystemVerilog/Verilog RTL design

Simulator tools

Python/Perl/TCL scripting

Independence and quick learning

Communication & project management

Logic design experience (ASIC/FPGA) 8+

Formação académica

BS EE

MSEE

Ferramentas

Questa/Incisive/VCS

Descrição da oferta de emprego

Rambus, a premier chip and silicon IP provider, seeks a Lead Member of Technical Staff (LMTS) – Logic Design to join our Silicon IP team in Hillsboro, Oregon. You will contribute to micro-architecture and RTL design for high-performance memory controllers for data centers and AI applications.

This role is an individual contributor reporting to the Director of Engineering, with a hybrid work model that includes on-site collaboration and some remote work.