Lead Logic Design Engineer: High-Perf Memory Controllers

Rambus.com; Hillsboro (OR); Híbrido; USD 180 000 - 260 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Hybrid work model

Resumo da oferta

Rambus, a premier chip and silicon IP provider, is seeking a Lead Member of Technical Staff – Logic Design to join our Silicon IP team in Hillsboro, Oregon. You will report to the Director of Engineering as an individual contributor and help define micro-architecture and RTL for next-generation memory controllers for data centers and AI applications.

This role offers a hybrid work model with three onsite days and two remote days, requiring strong collaboration with verification and physical

Qualificações

• 8+ years of logic design experience (ASIC/FPGA) with BSEE.

Responsabilidades

• Own micro-architecture definition and RTL design for schedulers, command pipelines, coherency/ordering logic and system interfaces
• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on data
• Collaborate closely with verification team to shape test plans and improve verification coverage
• Work with physical design team to understand and resolve timing, power, and congestion challenges
• Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary
• Provide technical support to FAE team on pre-sales customer engagements
• Provide technical support to AE team on post-sales customer deliveries

Conhecimentos

SystemVerilog/Verilog RTL design

Questa/Incisive/VCS

Python/Perl/TCL scripting

8+ years of logic design experience (S

Strong communication and project mgmt

Ability to learn quickly and work inde

AMBA AXI/CHI design experience

Formação académica

BSEE

MSEE

Ferramentas

Questa/Incisive/VCS

UVM

Descrição da oferta de emprego

Rambus, a premier chip and silicon IP provider, is seeking a Lead Member of Technical Staff – Logic Design to join our Silicon IP team in Hillsboro, Oregon. You will report to the Director of Engineering as an individual contributor and help define micro-architecture and RTL for next-generation memory controllers for data centers and AI applications.

This role offers a hybrid work model with three onsite days and two remote days, requiring strong collaboration with verification and physical