PE Logic Design

Rambus; Hillsboro (OR); Hybrid; USD 127,000 - 237,000; Full time

Job summary

Rambus in Hillsboro, Oregon seeks a Principal Logic Design Engineer to shape micro-architecture and RTL for next‑gen memory controllers for data centers and AI. You will drive PPA-driven design decisions and collaborate across verification, physical design, and customer engagements.

The role requires deep SystemVerilog/Verilog expertise, 10+ years of ASIC/FPGA experience, and a track record in complex memory interfaces. Hybrid work offers onsite and remote flexibility.

Qualifications

• Strong SystemVerilog/Verilog RTL design expertise.
• Questa/Incisive/VCS simulator experience.
• Python/Perl/TCL scripting experience.
• Ability to learn quickly and work independently.
• Solid communication and project management skills.
• 10+ years of logic design experience (ASIC/FPGA) with BS EE, or 8+ years with MS EE.

Responsibilities

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces.
• Analyze performance, power, and area trade-offs and drive design decisions based on quantitative data.
• Collaborate closely with verification team to shape test plans and improve verification coverage.
• Work with physical design team to understand and resolve timing, power, and congestion challenges.
• Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary.
• Provide technical support to FAE team on pre-sales customer engagements.
• Provide technical support to AE team on post-sale customer deliveries.

Skills

SystemVerilog RTL design

Simulation tools

Scripting (Python/Perl/TCL)

Independent learner

Communication & PM

ASIC/FPGA design experience

Education

Bachelor of Science in Electrical Engineering

Master of Science in Electrical Engineering

Tools

Questa/Incisive/VCS simulators

Job description

Overview

Rambus , a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our Silicon IP (SIP) team in Hills boro, Oregon. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro architecture and design of our next generation high performance and cutting edge memory controllers for data centers and AI applications. This is a fast growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you .

Rambus offers a flexible work environment, embracing a hybrid approach for most office based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities

• Own m icro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency /ordering logic and system interfaces
• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data
• Collaborate closely with v erification team to shape test plans and improve verification coverage
• Work with p hysical d esign team to understand and resolve timing, power, and congestion challenges
• Work with v erification team on regression failure debug and root cause , and provide RTL fix if necessary
• Provide technical support to FAE team on pre-sales customer e ngagements
• Provide technical support to AE team on post-sale s customer deliveries

Qualifications

• Strong System Verilog/Verilog RTL design expertise
• Questa/Incisive/VCS simulator experience
• Python/Perl/T CL scripting experience
• Ability to learn quickly and work independently
• Solid communication and project management skills
• 10 + years of logic design experience (ASIC/FPGA) with BS EE, or
• 8+ years of logic design experience (ASIC/FPGA) with MSEE

Definite Plus

• ASIC synthesis, timing constraint, CDC/RDC experience
• UVM Verification experience
• Memory (HBM, LPDDR) expertise
• AMBA AXI or CHI design experience

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. The US salary range for this full-time position is $127,400 to $236,600 . Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work . Rambus is proud to be an Equal Employment Opportunity and Affiantive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .