Senior Verification Engineer - DDR/HBM Memory Controller

Rambus.com

Hillsboro (OR)

Híbrido

USD 127 000 - 237 000

Tempo integral

14 dias+

Uma candidatura completa num minuto

Currículo e carta de apresentação personalizados, prontos a enviar.

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Resumo da oferta

Rambus, a premier memory interface and silicon IP provider, seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP Verification team in Hillsboro, Oregon. The role focuses on pre-silicon RTL verification for DDR, HBM, and GDDR controller tech within a hybrid work environment.

The successful candidate will perform testbench development, coverage planning, regression testing, and verification environment scripting, contributing to leading-edge memory technologies.

Qualificações

  • Bachelor's Degree or above in EE/CS.
  • Minimum 10 years experience with HDL verification.
  • SystemVerilog testbench and Verilog/SystemVerilog RTL fluency required.
  • DDR DRAM technology familiarity preferred.
  • Python and TCL scripting experience preferred.

Responsabilidades

  • Testbench and test sequence development for verification of new controller technologies and features
  • Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
  • Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
  • Development & support of Verification environment scripting and capabilities

Conhecimentos

HDL verification
DDR memory tech familiarity

Formação académica

Bachelor's degree in EE/CS

Ferramentas

Verilog
SystemVerilog
Python
TCL

Descrição da oferta de emprego

Rambus, a premier memory interface and silicon IP provider, seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP Verification team in Hillsboro, Oregon. The role focuses on pre-silicon RTL verification for DDR, HBM, and GDDR controller tech within a hybrid work environment.

The successful candidate will perform testbench development, coverage planning, regression testing, and verification environment scripting, contributing to leading-edge memory technologies.

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