Lead IP & SoC Verification Engineer

Microchip Technology Inc.; Chandler (AZ); On-site; USD 140,000 - 210,000; Full time

Job summary

Microchip Technology Inc. in Chandler, Arizona, seeks a Principal Engineer – Verification to lead IP-level verification for dsPIC products using formal verification and UVM testbenches.

You will collaborate with teams across the USA, India, and global groups to ensure high-quality results and timely execution. The role requires 10+ years in functional verification, strong SystemVerilog/UVM expertise, and experience building IP/SoC verification environments.

Qualifications

• Bachelor’s or Master’s degree in Electrical, Electronics, Computer Engineering or related field.
• 10+ years of functional verification experience.
• Strong SystemVerilog, assertions, and UVM knowledge.

Responsibilities

• Architect, develop, and maintain UVM verification environments.
• Define verification plans with constrained-random UVM testbenches and formal testbenches.
• Develop assertions and coverage in SystemVerilog and drive coverage closure.
• Debug RTL and testbench issues and coordinate with design teams to resolve defects.
• Integrate IP-level testbenches into SoC verification environments.
• Verify IP and product requirements with cross-functional teams and deliver on schedule.
• Provide mentoring to verification engineers and drive projects to completion.
• Improve methodologies with AI/ML automation to reduce verification cycle time.

Skills

SystemVerilog

UVM

Formal verification

RTL design

ARM architectures

Teamwork

Problem-solving

Education

Bachelor’s or Master’s in Electrical/Electronics/Computer Engineering

Tools

UVM testbenches

SystemVerilog Assertions

Job description

Microchip Technology Inc. in Chandler, Arizona, seeks a Principal Engineer – Verification to lead IP-level verification for dsPIC products using formal verification and UVM testbenches.

You will collaborate with teams across the USA, India, and global groups to ensure high-quality results and timely execution. The role requires 10+ years in functional verification, strong SystemVerilog/UVM expertise, and experience building IP/SoC verification environments.