PCB Layout Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Acceler8 Talent is hiring a PCB Layout Engineer in Mountain View, CA to own high-speed, high-power board designs from layout to fabrication release.

You will work with SI/PI, packaging and hardware teams to resolve constraints, develop power-delivery layouts, and ensure manufacturability for accelerator-class systems.

Qualifications

• Eight+ years of PCB layout experience on server/network/accelerator-class systems.
• Constraint-driven layout for complex high-speed, high-current boards.
• Expertise in impedance, stackup, return-path, crosstalk, and via optimization.

Responsibilities

• Own board-level physical design including stackup, impedance, placement and high-speed routing.
• Develop power-delivery layouts supporting high currents and large BGA footprints.
• Drive design-for-manufacture with fabrication and contract manufacturing partners.
• Collaborate with SI/PI, packaging and hardware teams to close constraints.

Skills

PCB layout

High-speed routing

Impedance control

Return-path management

Crosstalk management

Via optimization

Fabrication releases

Team collaboration

Tools

Cadence Allegro

Siemens Xpedition

Altium

Job description

We’re working with an early-stage AI compute company developing a full-stack platform built around system-on-wafer architecture and advanced 3D integration. The aim is to reduce the power, latency and infrastructure costs associated with moving data across conventional AI clusters.

The hardware challenge extends beyond silicon into the boards and systems that connect, power and support the accelerators.

They’re hiring a PCB Layout Engineer to own high-speed, high-power board designs from placement through fabrication release, working closely with packaging, signal and power integrity, and hardware systems engineers.

The role

• Own board-level physical design, including stackup and impedance definition, placement, high-speed routing, and fabrication and assembly release packages.
• Develop high-current power-delivery layouts supporting hundreds of amps and escape routing for large, fine-pitch accelerator BGAs.
• Implement complex routing constraints covering controlled impedance, return paths, crosstalk, length and skew matching, and via structures.
• Work with SI/PI, packaging and hardware systems teams to resolve constraints across the package-to-board interface.
• Drive design for manufacture and assembly with PCB fabrication and contract manufacturing partners.

Your experience

• At least eight years of PCB layout experience on server, networking or accelerator-class systems with high layer counts.
• Strong practical experience in constraint-driven layout for complex high-speed, high-current boards.
• Expertise in controlled impedance, stackup definition, return-path and crosstalk management, length and skew matching, and via optimization.
• Hands-on experience with Cadence Allegro, Siemens Xpedition, Altium or equivalent layout tools.
• Experience producing fabrication and assembly releases using formats such as Gerber, ODB++ or IPC-2581.
• A track record of working closely with SI/PI, packaging and hardware systems engineers to implement and close complex constraint sets.
• Experience with advanced package interfaces, chiplets, HBM, rigid-flex, backplanes, CAD automation or fabrication partner management would be useful but is not essential.

You’ll own the physical board designs that turn a new AI accelerator platform into working systems. Your decisions will affect signal quality, power delivery, manufacturability and how the hardware performs in the lab.

The role offers direct collaboration with silicon packaging and systems engineers, alongside responsibility for the designs that fabrication and assembly partners build.

This is an opportunity for someone who wants to take complex boards from layout through manufacturing release and stay involved when the hardware comes back.