Lead Full-Chip PV Engineer: Tapeout Ready

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal Physical Verification Engineer in San Jose, CA. You will lead the full-chip PV effort, own execution plans, and drive milestones toward tapeout readiness.

Collaborate with analog and IP teams to ensure clean integration and use ICV/Calibre tools to validate DRC/ERC/LVS results. The role requires a Bachelor’s or Master’s in Electrical Engineering and 7+ years of full-chip PV experience, with Tcl/Python scripting and strong cross-functional

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications.

Responsibilities

• Lead full chip Physical Verification effort and own execution plans.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks.
• Ownership of full chip verification and collaboration with analog IP teams for clean integration.
• Run and analyze DRC/ERC/LUP/PERC results and ensure readiness for tapeout.
• Provide early guidance on corner case requirements and influence floorplanning constraints.

Skills

Full-Chip PV

Leadership

Scripting (Python/Tcl)

Cross-functional Collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

ICV

Calibre

DRC tools

LVS tools

Job description

Celero Communications, Inc. is seeking a Principal Physical Verification Engineer in San Jose, CA. You will lead the full-chip PV effort, own execution plans, and drive milestones toward tapeout readiness.

Collaborate with analog and IP teams to ensure clean integration and use ICV/Calibre tools to validate DRC/ERC/LVS results. The role requires a Bachelor’s or Master’s in Electrical Engineering and 7+ years of full-chip PV experience, with Tcl/Python scripting and strong cross-functional