Principal Physical Verification Engineer

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal Physical Verification Engineer in San Jose, CA. You will lead the full-chip PV effort, own execution plans, and drive milestones toward tapeout readiness.

Collaborate with analog and IP teams to ensure clean integration and use ICV/Calibre tools to validate DRC/ERC/LVS results. The role requires a Bachelor’s or Master’s in Electrical Engineering and 7+ years of full-chip PV experience, with Tcl/Python scripting and strong cross-functional

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications.

Responsibilities

• Lead full chip Physical Verification effort and own execution plans.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks.
• Ownership of full chip verification and collaboration with analog IP teams for clean integration.
• Run and analyze DRC/ERC/LUP/PERC results and ensure readiness for tapeout.
• Provide early guidance on corner case requirements and influence floorplanning constraints.

Skills

Full-Chip PV

Leadership

Scripting (Python/Tcl)

Cross-functional Collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

ICV

Calibre

DRC tools

LVS tools

Job description

Principal Physical Verification Engineer

• San Jose, CA

Principal Full-Chip Physical Verification EngineerKey ResponsibilitiesTeam & Project Leadership

• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks

Physical Verification Ownership

• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules

Cross-Functional Collaboration

• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications

Proven hands-on experience with:

• Physical Verification tool (ICV/Calibre)
• Able to assemble a flow to support block/chip level PV

Strong expertise in:

• Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration

Preferred Qualifications

• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)

Javier Leon
Talent Acquisition
619-227-3193 cell/text
[e-mail]
www.celero.inc