Senior Full-Chip PV Engineer - Drive Tapeouts & Quality

Celero Communications; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Full-Chip Physical Verification Engineer to join our Physical Design team in San Jose, CA (HQ in Irvine). You will own all aspects of PV execution on advanced nodes, driving quality, tapeout readiness and timely delivery of complex digital blocks.

The ideal candidate has 7+ years of full-chip PV experience, hands-on with ICV/Calibre, and a proven ability to lead cross-functional verification efforts across projects and tapeout milestones.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience in full-chip verifications.
• Experience with ICV or Calibre and assembling PV flows.
• Strong floorplanning and DRC/LVS guidance.

Responsibilities

• Lead full-chip PV effort and develop execution plans.
• Drive tapeout readiness and milestone accountability.
• Collaborate with analog, block, and chip top teams.
• Run and analyze PV checks for DRC/ERC/LUP/PERC.

Skills

Full-chip PV experience

PV leadership

Automation scripting (Tcl/Python/Shell

Cross-functional collaboration

Floorplanning guidance

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

ICV/Calibre tools

PV tooling flow development

Job description

Celero Communications, Inc. is seeking a Full-Chip Physical Verification Engineer to join our Physical Design team in San Jose, CA (HQ in Irvine). You will own all aspects of PV execution on advanced nodes, driving quality, tapeout readiness and timely delivery of complex digital blocks.

The ideal candidate has 7+ years of full-chip PV experience, hands-on with ICV/Calibre, and a proven ability to lead cross-functional verification efforts across projects and tapeout milestones.