Lead Digital Verification Engineer (FPGA/SoC)

Teradyne; Tualatin (OR); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Health benefits

Dental plan

Vision plan

Retirement plan

Paid vacation

Job summary

Teradyne, a global test and automation specialist, is seeking a digital functional verification technical lead in Tualatin, Oregon. You will plan, strategize, and execute challenging FPGA verification projects and provide technical leadership for large cross-site teams.

Interface with hardware, software and applications groups, mentor junior engineers, and drive verification from Design Specification Review to closure using SystemVerilog, UVM, assertions, and coverage-driven techniques.

Qualifications

• Master’s or Bachelor’s in Electrical/Computer Engineering, Computer Engineering, or Computer Science with extensive related work experience.
• Experience with verification planning and testbench architecture.
• Experience with the complete functional verification cycle from design spec to closure.
• Proficiency in SystemVerilog constraints, randomization, assertions, and coverage.
• Expertise with UVM testbench development and Verification IP integration.

Responsibilities

• Lead digital verification projects and guide cross-site teams.
• Collaborate with hardware, software, and applications groups.
• Drive verification from planning to closure using modern methodologies.

Skills

SystemVerilog

UVM

Assertions

Functional Coverage

Constraint Random Testing

Verification Planning

Testbench Architecture

IP Integration

Python

Git

SV Debugging

Leadership

Education

Master's degree in Electrical/Computer Engineering or related

Bachelor's degree in Electrical/Computer Engineering or related

Tools

Git

SVN

ClearCase

TCL

Perl

Python

Job description

Teradyne, a global test and automation specialist, is seeking a digital functional verification technical lead in Tualatin, Oregon. You will plan, strategize, and execute challenging FPGA verification projects and provide technical leadership for large cross-site teams.

Interface with hardware, software and applications groups, mentor junior engineers, and drive verification from Design Specification Review to closure using SystemVerilog, UVM, assertions, and coverage-driven techniques.