Digital Verification Engineer Lead

Teradyne; Tualatin (OR); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Health benefits

Dental plan

Vision plan

Retirement plan

Paid vacation

Job summary

Teradyne, a global test and automation specialist, is seeking a digital functional verification technical lead in Tualatin, Oregon. You will plan, strategize, and execute challenging FPGA verification projects and provide technical leadership for large cross-site teams.

Interface with hardware, software and applications groups, mentor junior engineers, and drive verification from Design Specification Review to closure using SystemVerilog, UVM, assertions, and coverage-driven techniques.

Qualifications

• Master’s or Bachelor’s in Electrical/Computer Engineering, Computer Engineering, or Computer Science with extensive related work experience.
• Experience with verification planning and testbench architecture.
• Experience with the complete functional verification cycle from design spec to closure.
• Proficiency in SystemVerilog constraints, randomization, assertions, and coverage.
• Expertise with UVM testbench development and Verification IP integration.

Responsibilities

• Lead digital verification projects and guide cross-site teams.
• Collaborate with hardware, software, and applications groups.
• Drive verification from planning to closure using modern methodologies.

Skills

SystemVerilog

UVM

Assertions

Functional Coverage

Constraint Random Testing

Verification Planning

Testbench Architecture

IP Integration

Python

Git

SV Debugging

Leadership

Education

Master's degree in Electrical/Computer Engineering or related

Bachelor's degree in Electrical/Computer Engineering or related

Tools

Git

SVN

ClearCase

TCL

Perl

Python

Job description

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Date: Aug 15, 2026

Location: Tualatin, OR, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thoughtandin our workforce. Our employees aresupportedto innovateandlearnsomething new every day.

We cultivate a culture of inclusion for all employees that respectstheir individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drivesinnovationand delivers better business results.

Opportunity Overview

Act as a digital functional verification technical lead responsible for the planning, strategy, and execution of challenging FPGA verification projects. Provide technical leadership for large, cross-site verification teams. The position requires interfacing with other functional groups (e.g. hardware, software, applications).

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’reready to join usinthis mission, take a closer look at theminimumcriteria for the position.

• Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 10 years of relevant work experience OR Bachelor’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 12 years of relevant work experience
• Experience with verification planning and testbench architecture
• Experience with complete functional verification cycle from Design Specification Review to verification closure
• Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification
• Expertise with UVM testbench development and Verification IP integration
• Experience with Reference models development and integration
• Knowledge of at least one of the following protocols/technologies: Ethernet, PCIe, AXI, MIPI, DRAM, FLASH
• Experience with regression failures analysis
• Experience with verification progress tracking
• Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)
• Experience working with revision source control (e.g. clearcase, git, svn)
• Ability to track and bring issues to closure. Detailed oriented. Excellent planning and organizational skills.
• Experience leading verification team
• Experience working with teams located in different time zones
• Experience mentoring junior engineers

Desired (but not required) skills/experience:

• Experience in FPGA design implementation with System Verilog
• Experience in verification of Automated Test Equipment functionality
• Static and/or dynamic Formal Verification
• Experience with GVP source control continuous integration tool

Compensation

The base salary range for this role is$154,900 - $247,800 .This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details

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