Lead Digital Verification Engineer - ASIC Serdes

Ciena Corporation; Town of Victor (NY); On-site; USD 147,000 - 235,000; Full time

Benefits offered by this job

401(k) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays

Paid vacation and leave

Job summary

Ciena is seeking an expert digital verification engineer to verify the Wavelogic family in Rochester, NY. You will design and implement verification strategies, simulate and validate blocks, cores, and subsystems, and collaborate with a team of engineers and architects to ensure high-quality Serdes coverage.

The role requires strong SystemVerilog/UVM/SVA knowledge, excellent problem-solving, and the ability to lead focused groups.

Qualifications

• Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree with expert level experience in SystemVerilog, UVM, SVA and simulators from major vendors.
• Proven ability in determining appropriate and comprehensive digital verification and coverage strategies.
• Highly motivated self-starter, able to work independently, while being a great teammate.
• Ability to methodically address (debug) sophisticated technical problems.
• Excellent organization, written and oral English communication skills.

Responsibilities

• Understand project architecture and requirements to communicate with systems engineers and architects.
• Validate entire subsystems using simulation, formal and coverage methods.
• Create, review and optimize simulation environments, test cases and coverage plans.
• Lead or mentor groups and manage priorities toward objective delivery.
• Estimate schedules and provide status updates; report to Senior Manager as needed.
• Verify digital portion of Serdes and collaborate with partner teams for full coverage.

Skills

SystemVerilog

UVM

SVA

Digital verification strategy

Simulation

Collaboration

Education

Bachelor's degree in Electrical or Computer Engineering / CS

Tools

Jira

Git

Python

Job description

Ciena is seeking an expert digital verification engineer to verify the Wavelogic family in Rochester, NY. You will design and implement verification strategies, simulate and validate blocks, cores, and subsystems, and collaborate with a team of engineers and architects to ensure high-quality Serdes coverage.

The role requires strong SystemVerilog/UVM/SVA knowledge, excellent problem-solving, and the ability to lead focused groups.