Early-Career SerDes Verification Engineer (Remote)

Embedded Shishya; United States; Remote; USD 13,000 - 22,000; Full time

Job summary

Altera is seeking a talented, self-motivated engineer for our Design Verification team in Iași, Romania (Remote). You''ll work on high-speed SerDes IP verification across PCIe, Ethernet, and other interfaces, gaining deep technical expertise in digital and analog verification as you contribute to production silicon.

As an early-career engineer, you will develop SystemVerilog/UVM testbenches, write coverage models, analyze failures, and collaborate with design, architecture, and analog teams,

Qualifications

• BSc in Electrical Engineering, Computer Engineering, or equivalent.
• 0–5 years in digital design or verification (internships, academic projects, or industry).
• Working knowledge of SystemVerilog and basic familiarity with UVM concepts.
• Strong digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing.
• Strong analytical and debug mindset with good English communication.
• Preference for Iași resident.

Responsibilities

• Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks.
• Write testbenches, functional coverage models, and assertions.
• Run simulations, analyze failures, and debug RTL/testbench issues.
• Collaborate with design, architecture, and analog teams on block-level and top-level verification.

Skills

SystemVerilog

UVM

Testbenches

RTL Debugging

Digital design

Education

BSc in Electrical Engineering

Tools

SystemVerilog

UVM concepts

Job description

Altera is seeking a talented, self-motivated engineer for our Design Verification team in Iași, Romania (Remote). You''ll work on high-speed SerDes IP verification across PCIe, Ethernet, and other interfaces, gaining deep technical expertise in digital and analog verification as you contribute to production silicon.

As an early-career engineer, you will develop SystemVerilog/UVM testbenches, write coverage models, analyze failures, and collaborate with design, architecture, and analog teams,