Lead Die-to-Die Interconnect Modeling Architect

Broadcom; San Jose (CA); On-site; USD 168,000 - 268,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company matching

Employee stock purchase program (ESPP)

Job summary

Broadcom is seeking a senior system modeling and architecture engineer in San Jose, CA to develop comprehensive behavioral and architectural models predicting complete link behavior before implementation.

You will use MATLAB, Python, SystemC, or equivalent tools to build system-level models, assess BER, latency, throughput, and power, and guide design from concept to silicon. This role requires leadership across architecture, analog, digital, firmware, and packaging teams.

Qualifications

• Deep understanding of communication theory, equalization, and adaptive algorithms.
• Experience in high-speed SerDes or D2D communication systems architecture.
• Extensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools.
• Experience with architecture model to RTL to verification.
• Experience leading architectural verification, silicon correlation, and performance validation across multidisciplinary teams.

Responsibilities

• Develop comprehensive behavioral and architectural models that predict link behavior.
• Build system-level models using MATLAB, Python, SystemC, or equivalent environments.
• Predict link performance including BER, latency, throughput, and power consumption.
• Collaborate with implementation teams to ensure timing assumptions are achievable in silicon.
• Define architectural verification strategies and drive correlation between models and silicon.

Job description

Broadcom is seeking a senior system modeling and architecture engineer in San Jose, CA to develop comprehensive behavioral and architectural models predicting complete link behavior before implementation.

You will use MATLAB, Python, SystemC, or equivalent tools to build system-level models, assess BER, latency, throughput, and power, and guide design from concept to silicon. This role requires leadership across architecture, analog, digital, firmware, and packaging teams.