Principal Die-to-Die Interconnect Modeling Architect

Broadcom; San Jose (CA); On-site; USD 168,000 - 268,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company matching

Employee stock purchase program (ESPP)

Job summary

Broadcom is seeking a senior system modeling and architecture engineer in San Jose, CA to develop comprehensive behavioral and architectural models predicting complete link behavior before implementation.

You will use MATLAB, Python, SystemC, or equivalent tools to build system-level models, assess BER, latency, throughput, and power, and guide design from concept to silicon. This role requires leadership across architecture, analog, digital, firmware, and packaging teams.

Qualifications

• Deep understanding of communication theory, equalization, and adaptive algorithms.
• Experience in high-speed SerDes or D2D communication systems architecture.
• Extensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools.
• Experience with architecture model to RTL to verification.
• Experience leading architectural verification, silicon correlation, and performance validation across multidisciplinary teams.

Responsibilities

• Develop comprehensive behavioral and architectural models that predict link behavior.
• Build system-level models using MATLAB, Python, SystemC, or equivalent environments.
• Predict link performance including BER, latency, throughput, and power consumption.
• Collaborate with implementation teams to ensure timing assumptions are achievable in silicon.
• Define architectural verification strategies and drive correlation between models and silicon.

Job description

Key Responsibilities

System Modeling and Performance Prediction

Develop comprehensive behavioral and architectural models that accurately predict complete link behavior before implementation. Build system-level models using MATLAB, Python, SystemC, or equivalent modeling environments. Model transmitter, receiver, package, channel, clocking, equalization, adaptation, and protocol interactions. Predict link performance including BER, latency, throughput, bandwidth density, power consumption, energy efficiency, and manufacturing margin. Perform architectural sensitivity analyses across process, voltage, temperature (PVT), aging, package variation, jitter, noise, and channel impairments. Apply communication theory to help develop robust, high-performance signaling architectures. Analyze equalization, timing recovery, clock recovery, calibration, and adaptive signal processing algorithms. Evaluate convergence behavior, numerical stability, hardware efficiency, and implementation feasibility. Guide algorithm development from mathematical concepts through production silicon implementation. Model deterministic and random timing uncertainties including jitter, skew, supply noise, process variation, and environmental effects. Establish margin methodologies that ensure robust operation across manufacturing and operating conditions. Collaborate with implementation teams to ensure timing assumptions are achievable in silicon.

Architectural Verification and Silicon Correlation

Define the architectural verification strategy to ensure system requirements are traceable from concept through production silicon. Develop behavioral reference models that serve as the golden standard for RTL implementation, verification, software development, and silicon validation. Establish architecture-level performance metrics, verification methodologies, and success criteria. Drive correlation between behavioral models, RTL simulation, laboratory characterization, and production silicon. Validate architectural assumptions through simulation and silicon measurements, identifying performance gaps and driving corrective actions. Develop verification methodologies that account for implementation effects including finite precision, analog non-idealities, and hardware constraints. Define comprehensive validation strategies covering nominal operation, corner cases, interoperability, and robustness across all operating conditions.

Technical Leadership

Provide technical leadership across architecture, analog, digital, firmware, packaging, signal integrity, verification, validation, and product engineering organizations. Lead architecture reviews and critical technical decision-making throughout the product lifecycle. Mentor engineers and architects in communication systems, modeling, and architecture development. Influence technology roadmaps and drive innovation in next-generation die-to-die communication systems.

Required Qualifications

MS in Electrical Engineering, Computer Engineering, and 15 or more years in related field experience; or PhD in Electrical Engineering, Computer Engineering, and 12 or more years in related field experience. Deep understanding of communication theory, equalization, and adaptive algorithms. Experience in high-speed SerDes, or D2D communication systems architecture. Extensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools. Experience with architecture model to RTL to verification Experience leading architectural verification, silicon correlation, and performance validation across multidisciplinary engineering teams.

Desired Qualifications

Demonstrated expertise in D2D, UCIe, or other short-reach die-to-die communication. Expertise in advanced packaging including silicon interposers, EMIB, hybrid bonding, and 3D integration. Management experience.

Compensation and Benefits

The annual base salary range for this position is USD 167,500.00 To USD 268,000.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package:

• Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.

The company follows all applicable laws for Paid Family Leave and other leaves of absence.