Senior D2D Interconnect Modeling Architect

Broadcom Inc.; San Jose (CA); On-site; USD 168,000 - 268,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

Job summary

Broadcom Inc. seeks a Modeling Architect to lead a technical team building and evolving a foundational modeling platform for die-to-die PHY designs. You will focus on communication theory, algorithm development, system-level modeling, and architectural verification with silicon correlation.

The role requires deep expertise in timing, margin budgeting, and cross-functional leadership, with responsibilities spanning model development, performance prediction, and verification across RTL and silicon.

Qualifications

• MS in Electrical Engineering or PhD with 12+ years in related field (or 15+ years for non-PhD).
• Deep understanding of communication theory, equalization, and adaptive algorithms.
• Experience with high-speed SerDes or D2D architectures.
• Extensive modeling experience using MATLAB, Python, SystemC, or equivalent.

Responsibilities

• Develop behavioral and architectural models to predict link behavior prior to implementation.
• Lead architecture reviews and drive verification from concept to production silicon.
• Perform verification with RTL simulations and silicon correlation.
• Mentor teams across architecture, analog/digital, and product engineering.
• Drive margin budgeting and timing analyses across PVT and environmental conditions.

Skills

Communication theory

High‑speed SerDes

MATLAB

Python

SystemC

RTL verification

Algorithm development

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

MATLAB

Python

SystemC

Job description

Broadcom Inc. seeks a Modeling Architect to lead a technical team building and evolving a foundational modeling platform for die-to-die PHY designs. You will focus on communication theory, algorithm development, system-level modeling, and architectural verification with silicon correlation.

The role requires deep expertise in timing, margin budgeting, and cross-functional leadership, with responsibilities spanning model development, performance prediction, and verification across RTL and silicon.