Lead Design Engineer

Cadence Design Systems; Austin, Northern (TX, KY); On-site; USD 120,000 - 180,000; Full time

Job summary

Cadence Design Systems seeks a verification professional to define the overall verification strategy and architecture for complex SoC projects. You will design scalable testbenches, BFMs, monitors, scoreboards, and checkers, while leading debugging and root-cause analysis with design teams.

You will drive constrained-random testing and formal verification to improve coverage and quality. With 4–7 years of DV experience, you will mentor juniors, collaborate across design, architecture, and

Qualifications

• Experience in DV verification methodologies and verification planning.
• Ability to design scalable testbenches and BFMs.
• Proven track record in debugging complex design bugs and leading root-cause analysis.

Responsibilities

• Define the verification strategy and methodology for projects.
• Architect scalable verification environments with BFMs, monitors, scoreboards, and checkers.
• Develop and execute complex test cases and sequences for high coverage.
• Lead debugging and root-cause analysis with design engineers.
• Implement constrained-random stimulus and constraint sets.
• Apply formal techniques to prove properties and find deep bugs.
• Manage coverage analysis and sign-off for verification phase.

Skills

Strategy & architecture

Technical leadership

Mentorship

Cross-functional collaboration

Education

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field

Tools

UVM/SystemVerilog

Formal verification tools

Job description

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**Core Responsibilities* Strategy and ArchitectureVerification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.* Execution and Technical LeadershipDevelopment: Write complex test cases and sequences to achieve high functional coverage.Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.Formal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.* Metric ManagementCoverage Analysis: Monitor and analyze functional and code coverage metrics.Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.Sign-off: Define the \"definition of done\" and provide final technical approval for the verification phase.* Soft Skills and LeadershipMentorship: Guiding junior engineers on coding standards and debugging techniques.Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.Required QualificationsB.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field4–7 years of hands-on DV experience in semiconductor/ASIC/SoC companies