Lead Design Engineer

Cadence; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence is hiring a digital design engineer to design and integrate IPs in SoC based on high‑level customer specifications. You will run lint/CDC checks, create synthesis constraints, and perform basic synthesis for PPA optimization to meet power, performance and area targets.

You will develop detailed microarchitectural specifications, support the verification team with test plans and coverage, assist the physical design team, and devise automated solutions for repetitive tasks.

Qualifications

• 5–8 years of experience as a digital design engineer.
• Proficient in Verilog/SystemVerilog and digital design fundamentals.
• Experience with Lint/CDC, synthesis constraints, and STA.

Responsibilities

• Design and integration of IPs in SoC from customer specs.
• Perform Lint/CDC checks and resolve related issues.
• Create synthesis constraints and perform basic synthesis for PPA optimization.
• Create detailed Microarchitectural Specification documents.
• Support verification with test plans, coverage analysis, and debugging.
• Support physical design team for implementation needs.
• Implement automated solutions to reduce repetitive tasks.
• Collaborate across teams for effective project execution.

Skills

Digital design fundamentals

Verilog/SystemVerilog

Scripting (Python/Perl/Tcl)

Communication skills

Education

B.E./B.Tech/M.Tech in Digital Design

Tools

Lint/CDC tools

Synthesis tools

STA

Xcelium/Verisium

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities:

• Design and integration of IPs in SoC based on high-level architectural specifications from customers.
• Perform Lint/CDC checks on the design for quality assurance and resolve related issues.
• Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.
• Create detailed Microarchitectural Specification documents for the design.
• Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.
• Provide support to the physical design team as needed for design implementation.
• Implement innovative solutions to automate repetitive tasks.
• Collaborate within and across teams for effective project execution.

Requirements:

• B.E./B.Tech/M.Tech with 5-8 years of experience as a digital design engineer.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).
• Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.
• Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.
• Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.
• Experience with AMBA protocols and other ARM IPs is a plus.
• Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.
• Proficiency in scripting languages (Python/Perl/Tcl).
• Ability to innovate and automate repetitive tasks.
• Good communication skills for effective cross-functional collaboration.

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