Lead Circuit Design Engineer – High-Performance ASICs

Socket.dev; Beaverton (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

Socket.dev in Beaverton, Oregon, is seeking a Circuit Design Engineering Lead to spearhead state-of-the-art standard cell development for ASICs. You will lead a small team, drive PPA improvements, and collaborate with CPU, SOC, and GPU teams to deliver fast, reliable silicon solutions.

You will influence design methodologies, participate in DRM/IPDK processes, and mentor engineers across disciplines while shaping the next generation of circuit technology for high-performance devices.

Qualifications

• Bachelor's Degree + minimum of 3 years of experience.
• 3+ years of experience in Standard cells circuit development.
• Proven experience leading & mentoring a small team.
• Strong influence and interpersonal skills; able to work with multi-functional teams.
• Knowledge of standard cell layout and PDV-related flows.

Responsibilities

• Drive development of high performance, low power standard cells to improve design PPA.
• Drive development of optimal level shifters and retention designs for low power design.
• Identify next generation ideas to drive PPA improvements.
• Engage with CPU, SOC and GPU teams on chip level integration requirements.
• Drive circuit QA checks and analytics; develop new methodologies for new design requirements.
• Work with foundries on DRM compliant layout checkers and iPDK requirements.
• Plan and drive development of new circuits and tech node enablement.
• Manage migration to new PDK, PDV of standard cells and releases.

Skills

Standard cells circuit development

Leadership/mentoring

Interpersonal skills

Scripting Perl/TCL

Cross-functional collaboration

Team influence

Education

Bachelor's degree

Tools

Virtuoso

DRM

DRC/LVS decks

PDV flows

Job description

Socket.dev in Beaverton, Oregon, is seeking a Circuit Design Engineering Lead to spearhead state-of-the-art standard cell development for ASICs. You will lead a small team, drive PPA improvements, and collaborate with CPU, SOC, and GPU teams to deliver fast, reliable silicon solutions.

You will influence design methodologies, participate in DRM/IPDK processes, and mentor engineers across disciplines while shaping the next generation of circuit technology for high-performance devices.