Lead ASIC DFT Staff Engineer

Best NanoTech; United States; Remote; USD 170,000 - 210,000; Full time

Job summary

Best NanoTech is seeking a Lead ASIC DFT Staff Engineer to own DFT architecture, implementation, verification, timing simulation, and debug for complex ASIC and SoC designs. The role requires hands-on expertise in Scan, ATPG, MBIST, DFT timing simulations, SDF/SDC, pattern retargeting, and post-silicon validation.

The engineer will collaborate with RTL, verification, physical design, STA, and silicon validation teams to achieve sign-off and successful silicon bring-up.

Qualifications

• 10+ years of hands-on ASIC/SoC Design-for-Test (DFT).
• End-to-end ownership of DFT implementation on complex ASIC/SoC designs.
• Strong understanding of DFT fundamentals, fault models, test coverage, ATPG, diagnosis, and manufacturing test concepts.

Responsibilities

• Lead end-to-end DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Own scan architecture, scan insertion, scan chain stitching, and scan compression implementation.
• Develop and execute ATPG flows, including pattern generation, fault simulation, coverage analysis, and pattern validation.

Skills

Scan architecture

ATPG

MBIST

LBIST

DFT timing

SDF/SDC

Pattern retargeting

DFT analysis

DFT debug

Post-silicon validation

TCL scripting

Tools

Synopsys DFTMAX

TetraMAX

Mentor tools

Cadence tools

Job description

Role Overview

Work Mode: Remote; must be available to work aligned with PST time zone

Experience: 10+ years of hands-on ASIC Design-for-Test (DFT) experience

Engagement: Contract

Visa: Open to candidates with valid U.S. work authorization

We are looking for an experienced Lead ASIC DFT Staff Engineer to own DFT architecture, implementation, verification, timing simulation, and debug for complex ASIC and SoC designs.

The role requires strong hands-on expertise in Scan, ATPG, MBIST, DFT timing simulations, SDF, SDC, pattern retargeting/porting, DRC, diagnosis, and post-silicon validation. The engineer will work closely with RTL, verification, physical design, STA, and silicon validation teams through implementation, sign-off, and silicon bring-up.

Key Responsibilities

• Lead end-to-end DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Own scan architecture, scan insertion, scan chain stitching, and scan compression implementation.
• Develop and execute ATPG flows, including pattern generation, fault simulation, coverage analysis, and pattern validation.
• Implement, integrate, verify, and debug MBIST and LBIST solutions.
• Perform ATPG timing simulations using SDF-annotated gate-level netlists and resolve simulation failures.
• Develop and validate DFT SDC constraints, timing requirements, and DFT-specific timing checks.
• Perform DFT DRC analysis, debug violations, and drive closure before sign-off.
• Support pattern retargeting and pattern porting across IP, subsystem, and SoC levels.
• Perform failure diagnosis, root-cause analysis, fault coverage debug, and post-silicon validation (PSV).
• Support JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
• Collaborate with RTL design, synthesis, LEC, physical design, STA, verification, and silicon validation teams to resolve DFT integration issues.
• Develop automation using TCL, Perl, or Python for DFT implementation, reporting, pattern processing, and debug.

Required Qualifications

• 10+ years of hands-on experience in ASIC/SoC Design-for-Test (DFT).
• Demonstrated end-to-end ownership of DFT implementation on complex ASIC or SoC designs.
• Strong understanding of DFT fundamentals, fault models, test coverage, ATPG, diagnosis, and manufacturing test concepts.
• Strong hands-on experience with scan insertion, ATPG, MBIST, DFT verification, timing simulation, and DRC closure.
• Experience with Synopsys DFTMAX / TetraMAX or equivalent production DFT tools.
• Hands-on experience with DFT tools from Synopsys, Siemens EDA/Mentor, or Cadence.
• Experience with large SoC designs, hierarchical DFT methodologies, and multi-clock/multi-power-domain environments.
• Good understanding of RTL, synthesis, LEC, STA, physical design, and timing closure as they relate to DFT.
• Experience supporting post-silicon debug, silicon bring-up, diagnosis, and failure analysis.
• Ability to independently own technical problems and work with geographically distributed engineering teams.