Application Specific Integrated Circuit Design Engineer

Technical-Link N. America; Brooklyn Park (MN); On-site; USD 140,000 - 210,000; Full time

Job summary

Technical-Link N. America seeks an ASIC Chip Lead and Design Engineer to drive the full chip design lifecycle from concept to implementation.

You will lead architecture, RTL, and physical design with a strong emphasis on area, power, and performance targets. The ideal candidate has 10+ years in ASIC/SoC design, hands-on RTL in Verilog/SystemVerilog, and extensive experience with Synopsys Design Compiler and EDA tools, plus exposure to radiation hardened and analog/mixed-signal design.

Qualifications

• Bachelors/Master’s in electrical engineering/computer science or equivalent.
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving skills and attention to detail.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to Mentor less senior engineers.

Responsibilities

• Lead the architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for the chip’s components.
• Use Synopsys Design Compiler to create RTL designs and optimize for area, power, and performance.
• Develop timing constraints for the entire chip and work with physical design teams on floorplanning, placement, and routing.
• Constrain and verify RISC processors within the chip and optimize performance and power.
• Coordinate with verification engineers to ensure functional correctness and testbenches.

Skills

Unix/Linux

Shell scripting

C/C++

PERL/Python/TCL

Windows apps

Education

Bachelor's/Master's in EE/CS

Tools

Synopsys Design Compiler

EDA tools

Job description

As an ASIC Chip Lead and Design Engineer, you will play a pivotal role in the development of custom-designed Application-Specific Integrated Circuits (ASICs). Your expertise will span the entire chip design lifecycle, from conceptualization to implementation. You’ll collaborate with cross-functional teams, ensuring successful chip development while adhering to performance, power, and area targets. The right candidate will be someone with high aptitude who is currently hands on designing complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. An ideal candidate will additionally have experience with radiationhardened design, analog/mixed-signal design and EDA, and std-cell library development.

Additional duties include the evaluation of customer requirements and estimates of effort/expenses for potential new business, and participation in identifying problems with and improvements to, internal design methodologies.

Essential Duties and Qualifications:

• Chip Architecture and Development:
• Lead the architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for the chip’s components.
• RTL Design and Synthesis:
• Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.
• Optimize RTL code for area, power, and performance.
• Implement and verify complex digital blocks.
• Constraint Development:
• Develop timing constraints for the entire chip.
• Work closely with physical design teams to ensure successful place-and-route. RISC Processor Conformance:
• Constrain and verify RISC processors within the chip. o Optimize processor performance and power efficiency.
• Physical Design Collaboration:
• Collaborate with physical design teams on floorplanning, placement, and routing.
• Address any design closure issues.
• Verification Support:
• Work with verification engineers to ensure functional correctness.
• Assist in creating testbenches and verifying the chip’s functionality.
• Modern revision-control tools and best-practices in a collaborative, multi-site design community.
• Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting.
• Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.

Qualifications:

• Bachelors/master’s in electrical engineering/computer science or equivalent.
• 10+ years of direct industry experience with ASIC and/or SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong understanding of digital design principles.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Excellent problem-solving skills and attention to detail.
• A strong background in RTL based digital IC design using Verilog/SystemVerilog Proven track record of first-pass successes.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Willingness to Mentor less senior engineers.
• Experience with industry standard development tools and methodologies.

Location:

• Work on-site at the TSS office in Brooklyn Park, MN.