Lead ASIC Design Engineer: Architect & RTL Expert

Technical Link LLC; Brooklyn Park (MN); On-site; USD 150,000 - 190,000; Full time

Job summary

Technical Link LLC in Minnesota is seeking an experienced ASIC Chip Lead and Design Engineer to guide the full ASIC/SoC design flow from architecture to verification. You will lead architectural decisions, define interfaces, and drive RTL design and synthesis using industry-standard tools.

The role requires hands-on leadership of cross-functional teams, including constraint development and physical design collaboration.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
• 10+ years of direct industry experience in ASIC and/or SoC design.
• Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
• Proficiency with Synopsys Design Compiler and other industry-standard EDA tools.
• Strong understanding of digital design principles and the complete ASIC/SoC design flow.
• Familiarity with RISC architectures, such as ARM or MIPS.
• Proven track record of first-pass silicon success.
• Excellent problem-solving skills and strong attention to detail.
• Self-starter with the ability to assume technical leadership responsibilities.
• Ability to work effectively within diverse, cross-functional engineering teams.
• Willingness and ability to mentor less experienced engineers.
• Experience with industry-standard development tools and methodologies.

Responsibilities

• Lead architectural design of ASICs based on high-level requirements and block diagrams.
• Collaborate with system architects to define chip functionality, interfaces, and performance targets.
• Develop detailed specifications for chip components.
• Use Synopsys Design Compiler to create and synthesize RTL designs.
• Optimize RTL code for area, power, and performance.
• Implement and verify complex digital blocks.
• Develop timing constraints for the entire chip.
• Work closely with physical design teams to ensure successful place-and-route.
• Constrain and verify RISC processors within the chip.
• Optimize processor performance and power efficiency.
• Collaborate with physical design teams on floorplanning, placement, and routing.
• Address design closure issues throughout development.
• Work with verification engineers to ensure functional correctness.
• Assist with testbench development and verification of chip functionality.
• Utilize UNIX/Linux environments and scripting (sed, awk, grep).
• Use languages like C/C++, Perl, Python, and Tcl.
• Work with Windows apps such as Word, Excel, PowerPoint, Visio, Project.

Skills

RTL Design

SystemVerilog

Verilog

EDA Tools

Synthesis

C/C++

Python

Tcl

UNIX/Linux

Education

Bachelor's or Master's degree in Electrical Engineering or related field

Tools

Synopsys Design Compiler

EDA Tools

Unix/Linux

Job description

Technical Link LLC in Minnesota is seeking an experienced ASIC Chip Lead and Design Engineer to guide the full ASIC/SoC design flow from architecture to verification. You will lead architectural decisions, define interfaces, and drive RTL design and synthesis using industry-standard tools.

The role requires hands-on leadership of cross-functional teams, including constraint development and physical design collaboration.