Lead ASIC Design Engineer - Onsite Brooklyn Park

Technical Link LLC; Brooklyn Park (MN); On-site; USD 145,000 - 205,000; Full time

Job summary

Technical Link LLC in Brooklyn Park, MN is seeking an ASIC Chip Lead to drive RTL and block-level design across the full design flow. This on-site role collaborates with cross-functional teams to meet performance, power, and area targets.

The ideal candidate has 10+ years in ASIC/SoC, strong Verilog/SystemVerilog, and hands-on experience with Synopsys Design Compiler and EDA tools. Mentors engineers and influences design methodologies.

Qualifications

• 10+ years of direct ASIC/SoC design experience.
• Strong RTL design and verification fundamentals.
• Proficiency with Synopsys Design Compiler and EDA tools.

Responsibilities

• Lead architectural design of ASICs from high-level requirements.
• Develop detailed chip specifications and interfaces.
• Own RTL design, synthesis, timing constraints, and place-and-route collaboration.
• Support verification, testbench creation, and design closure issues.
• Mentor junior engineers and participate in design methodologies.

Skills

UNIX/Linux

Shell scripting

C/C++

Python/TCL scripting

Verilog/SystemVerilog

RTL design

EDA tools

Synopsys Design Compiler

RISC architectures

Leadership

Education

Bachelor's or Master's in electrical engineering or computer science

Tools

Synopsys Design Compiler

EDA tools

Job description

Technical Link LLC in Brooklyn Park, MN is seeking an ASIC Chip Lead to drive RTL and block-level design across the full design flow. This on-site role collaborates with cross-functional teams to meet performance, power, and area targets.

The ideal candidate has 10+ years in ASIC/SoC, strong Verilog/SystemVerilog, and hands-on experience with Synopsys Design Compiler and EDA tools. Mentors engineers and influences design methodologies.