Lead ASIC Design Engineer - AI Accelerator & SoC

OHO Group (Lithuania); San Jose (CA); On-site; USD 180,000 - 360,000; Full time

Job summary

AI Accelerator Startup in the San Francisco Bay Area is seeking an experienced Lead ASIC Design Engineer with deep RTL and microarchitectural expertise to drive complex SoC projects. You will own RTL design and architecture, work on high-performance interconnects, and collaborate with verification, software and system teams throughout the silicon development cycle.

The ideal candidate has 10+ years of ASIC/SoC design experience, hands-on RTL development, and familiarity with PCIe, CXL or UCIe.

Qualifications

• 10+ years of ASIC/SoC design experience.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with PCIe, CXL or UCIe.

Responsibilities

• Own RTL design and microarchitecture.
• Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.
• Work closely with verification engineers on design validation, debugging and performance analysis.

Skills

RTL design

Microarchitecture

Interconnect protocols

Verification collaboration

Architecture collaboration

Education

Bachelor/Master/PhD in EE/CE/CS

Tools

PCIe

CXL

UCIe

Job description

AI Accelerator Startup in the San Francisco Bay Area is seeking an experienced Lead ASIC Design Engineer with deep RTL and microarchitectural expertise to drive complex SoC projects. You will own RTL design and architecture, work on high-performance interconnects, and collaborate with verification, software and system teams throughout the silicon development cycle.

The ideal candidate has 10+ years of ASIC/SoC design experience, hands-on RTL development, and familiarity with PCIe, CXL or UCIe.