ASIC Implementation Engineer PD

Broadcom

San Jose (CA)

On-site

USD 121,900 - 195,000

Full time

14 days+

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Benefits offered by this job

Discretionary bonus
Equity grant

Job summary

Broadcom is seeking an ASIC top level floorplan Physical Design Engineer to contribute to next‑generation AI and PCIe switch products. You will take RTL to silicon tape‑out, applying deep expertise in physical design across floorplanning, clocking, and integration.

Roles require hands‑on work at our San Jose site, with no remote option. The ideal candidate has 8+ years in top level floorplanning (or 6+ with a Master’s) and strong scripting with Python/Tcl/Perl, plus experience with EDA tools.

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering with extensive top level floorplanning experience.
  • Experience in die size estimation, partitioning, clocking and pin planning.
  • Background with Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet, etc.
  • Ability to resolve chip‑level DRC/LVS/EMIR issues for advanced nodes.
  • Proven bump planning, RDL implementation and multi‑voltage domain designs.
  • Experience with hierarchical floorplanning, power grid design and structured clocks.

Responsibilities

  • Own chip floor planning, partition creation, clock tree and delivery of top level partitions.
  • Resolve physical design issues related to chip integration and assembly.
  • Manage cross‑functional interactions related to top level floorplanning, I/O and bump planning with the package team.
  • Develop and improve floorplan implementation methodologies using industry and internal tools.
  • Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specifications.

Skills

Top-level floorplanning
Die size estimation
Partitioning
Clocking
Pin planning
Bump planning
RDL implementation
Voltage domain design
Hierarchical floorplanning
Power grid design
Python/Tcl/Perl
EDA tools
Vendor IP evaluations
DDR/SerDes/HBM

Education

Bachelor’s degree in Electrical Engineering
Master’s degree in Electrical Engineering

Tools

EDA tools

Job description

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Job Description

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the ASIC Products Division. This position involves working with the latest technology to drive next generation Artificial Intelligence and PCIe Switch Products. In this role you will take RTL to silicon tape‑out, requiring in‑depth knowledge and expertise in all Physical Design aspects.

Responsibilities
  • Own chip floor planning, partition creation, clock tree and delivery of top level partitions
  • Resolve physical design issues related to chip integration and assembly
  • Manage cross‑functional interactions related to top level floorplanning, I/O and bump planning with the package team
  • Develop and improve floorplan implementation methodologies using industry and internal tools
  • Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specifications
Preferred Qualifications
  • Bachelor’s degree in Electrical Engineering and 8+ years of experience in top level floorplanning with a focus on die size estimate, partitioning, clocking and pin planning
  • Or Master’s degree in Electrical Engineering and 6+ years of experience in the same focus areas
  • Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet, etc.)
  • Experience in resolving chip level DRC/LVS/EMIR issues for advanced nodes
  • Proven track record with bump planning, RDL implementation, and multi‑voltage domain designs
  • Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning
  • Experience collaborating with design, package and methodology teams during the development phase
  • Experience in scripting languages like Python, Tcl, or Perl and EDA tools
  • Must work in person at our San Jose site with no remote work option
Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 to USD 195,000.00.

As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive a new hire equity grant and annual equity awards, tying your success to the company’s growth. All subject to relevant plan documents and award agreements.

Broadcom offers a comprehensive benefits package: medical, dental and vision plans; 401(K) participation with company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company paid holidays; paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Equal Opportunity Statement

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

Additional Information

If you are located outside the USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom!

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

For more information, please visit our video library (http://www.broadcom.com/videos) and check out our Connected by Broadcom series.

Follow us on LinkedIn: https://www.linkedin.com/company/broadcom.

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