Lead SoC Design Engineer

Oho Group; San Francisco (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Oho Group in partnership with a well-funded stealth-mode technology company is seeking a Lead SoC Design Engineer in the San Francisco Bay Area for a next-generation edge AI SoC.

Joining as one of the first hardware hires, you will set technical direction for design, define microarchitecture, drive PPA trade-offs, lead RTL of key subsystems, and guide the team toward first tapeout with a hybrid work model and occasional travel.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• Experience designing complex ASICs and SoCs.
• Strong knowledge of AMBA protocols (AXI/AXI-S/APB) and ARM ecosystem.

Responsibilities

• Define and document SoC microarchitecture and collaborate with architecture, software, and verification teams.
• Drive performance, power and area (PPA) trade-offs to meet targets.
• Lead RTL implementation of key SoC subsystems and guide verification and tapeout.
• Ensure design quality through linting, CDCs, RDCs, SDC and timing closure.
• Coordinate with physical implementation and ensure timing/power targets are met.

Skills

ASIC design

AMBA AXI/AXI-S/APB

Power-domain design with UPF

SoC RTL implementation

Tapeout leadership

Education

Bachelor's or Master's in Electrical/Computer Engineering

Job description

Lead SoC Design Engineer - Stealth Startup - San Francisco Bay Area

We have partnered with a well-funded, stealth-mode technology company developing a next-generation computing platform built around a custom, high-performance edge SoC.

Joining as one of the first hardware hires, you'll be responsible for setting technical direction for the design of a high-performance edge-AI SoC, alongside building a team and leading to first tapeout.

You’ll also play a key role in defining the microarchitecture, making critical PPA trade-offs and leading the RTL implementation of key SoC subsystems.

What You’ll Do

• Define and document detailed SoC microarchitecture and work closely with architecture, software and verification teams.
• Drive performance, power and area (PPA) trade-offs to meet demanding product targets.
• Work with verification teams on test plans, emulation and first-pass silicon success.
• Own key design-quality activities including Lint, CDC, RDC, SDC and VCLP.
• Ensure designs can successfully progress through physical implementation while meeting frequency and power targets.

What We’re Looking For

• 10+ years’ experience developing complex ASICs, ideally on advanced process nodes.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent experience.
• Strong knowledge of AMBA protocols, particularly AXI, AXI-S and APB.
• Familiarity with the ARM ecosystem and/or cache-coherency protocols.
• Experience designing SoCs with multiple power domains and UPF.

This is a flexible role based in the San Francisco Bay Area. Although hybrid is preferred, there is openness to remote work from across the US with occasional travel into the Bay Area.