Senior ASIC Design Engineer

Vaspire Technologies Inc.; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Vaspire Technologies Inc. in Mountain View, CA is seeking a senior NoC RTL architect to design high-bandwidth IP for AI SoCs. You will define microarchitecture, write synthesizable Verilog/SystemVerilog, and push Synthesis, timing, CDC/Lint, and PPA to closure.

You will integrate IP across SoC subsystems, support post-silicon debug, and collaborate with architecture, verification, physical design, and SoC teams. Proficiency in Python for design automation is expected.

Qualifications

• 6+ years in digital design, RTL & microarchitecture.
• Strong Verilog/SystemVerilog and synthesis experience.
• Experience with NoC/interconnect, high-throughput/low-latency designs.
• SoC integration, post-silicon debug, Python scripting.

Responsibilities

• Design high-performance NoC IP for AI SoCs and define microarchitecture.
• Develop synthesizable RTL using Verilog/SystemVerilog and manage timing constraints, CDC/Lint, and PPA trade-offs.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC teams.
• Develop Python scripts for design automation.

Skills

RTL

SystemVerilog

NoC

PPA

Synthesis

CDC

Lint

Timing

Python

Job description

• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
• Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts for design automation and productivity.

Qualifications

• 6+ years of hands-on digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs.
• Experience with NoC/interconnect and high-throughput/low-latency designs.
• Experience with SoC integration, post-silicon debug, and Python scripting.

Key Skills: ASIC | NoC | RTL | SystemVerilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python