Lead Analog & RF IC Layout Engineer (Sunnyvale)

Capgemini Engineering; Santa Clara (CA); On-site; USD 73,000 - 174,000; Full time

Job summary

Capgemini Engineering in Sunnyvale, CA is seeking an experienced Analog and RF Layout Engineer to develop complex analog and mixed-signal ICs for advanced communications.

Lead layout implementation, floorplanning, routing, and chip assembly for 7nm FinFETs, collaborating across design and verification teams. The role emphasizes thermal-aware design and electromigration mitigation to ensure robust silicon.

Qualifications

• Bachelor’s degree in Electrical Engineering.
• 6+ years in analog and RF IC layout.
• High‑speed analog and mixed‑signal in advanced FinFET CMOS.
• Proficiency with Cadence, Mentor Graphics or Synopsys tools.
• Experience with transceivers, CMOS drivers, high-speed data converters, or PLLs.
• Floorplanning, routing, chip integration, and physical verification.

Responsibilities

• Lead layout implementation for analog and RF ICs in FinFET tech.
• Perform floorplanning, block routing, and top-level chip assembly; partner across teams.
• Optimize layouts for performance, manufacturability, reliability, and silicon quality.
• Apply thermal-aware design and electromigration mitigation techniques.
• Support physical verification, design reviews, and design-rule compliance.

Skills

Analog RF design

Floorplanning

Routing

Physical verification

EMI considerations

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Synopsys

Job description

Capgemini Engineering in Sunnyvale, CA is seeking an experienced Analog and RF Layout Engineer to develop complex analog and mixed-signal ICs for advanced communications.

Lead layout implementation, floorplanning, routing, and chip assembly for 7nm FinFETs, collaborating across design and verification teams. The role emphasizes thermal-aware design and electromigration mitigation to ensure robust silicon.