Lead 3D Stacked DRAM-on-Logic Design Engineer

SK hynix America; San Jose (CA); On-site; USD 150,000 - 260,000; Full time

Job summary

SK hynix America is seeking a 3D Stacked DRAM-on-Logic Design Engineer to strengthen leadership in DRAM-on-Logic through optimized die design. The role involves co-design with U.S.-based customers and close collaboration with foundries to deliver digital IP for 3D-stacked DRAM.

The job requires a Bachelor's degree in Electrical Engineering or related field and 5+ years of experience in RTL design, memory IP, and DFT/DFD.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering or a related field with 5+ years of relevant experience.
• Experience with Verilog/VHDL and RTL design for memory IP/SoC.
• Experience with memory controllers and DRAM DFT/DFD.
• Strong communication in English and ability to present to senior management.

Responsibilities

• Lead the co-design of 3D-stacked DRAM logic dies with U.S. customers.
• Provide digital IP services for 3D-stacked DRAM to enable 3D-stacked DRAM configurations.
• Collaborate with foundries to build digital IP for 3D-stacked DRAM.

Skills

Verilog

VHDL

RTL design

Memory controllers

BIST/DFT/DFD

PPA optimization

English communication

Education

Bachelor’s degree or higher in Electrical Engineering or related field

Job description

SK hynix America is seeking a 3D Stacked DRAM-on-Logic Design Engineer to strengthen leadership in DRAM-on-Logic through optimized die design. The role involves co-design with U.S.-based customers and close collaboration with foundries to deliver digital IP for 3D-stacked DRAM.

The job requires a Bachelor's degree in Electrical Engineering or related field and 5+ years of experience in RTL design, memory IP, and DFT/DFD.