3D Stacked DRAM-on-Logic Design Engineer

SK hynix America; San Jose (CA); On-site; USD 150,000 - 260,000; Full time

Job summary

SK hynix America is seeking a 3D Stacked DRAM-on-Logic Design Engineer to strengthen leadership in DRAM-on-Logic through optimized die design. The role involves co-design with U.S.-based customers and close collaboration with foundries to deliver digital IP for 3D-stacked DRAM.

The job requires a Bachelor's degree in Electrical Engineering or related field and 5+ years of experience in RTL design, memory IP, and DFT/DFD.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering or a related field with 5+ years of relevant experience.
• Experience with Verilog/VHDL and RTL design for memory IP/SoC.
• Experience with memory controllers and DRAM DFT/DFD.
• Strong communication in English and ability to present to senior management.

Responsibilities

• Lead the co-design of 3D-stacked DRAM logic dies with U.S. customers.
• Provide digital IP services for 3D-stacked DRAM to enable 3D-stacked DRAM configurations.
• Collaborate with foundries to build digital IP for 3D-stacked DRAM.

Skills

Verilog

VHDL

RTL design

Memory controllers

BIST/DFT/DFD

PPA optimization

English communication

Education

Bachelor’s degree or higher in Electrical Engineering or related field

Job description

3D Stacked DRAM-on-Logic Design Engineer

San Jose, CA

Job Title: 3D Stacked DRAM-on-Logic Design Engineer
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite

About SK hynix America: At SK hynix America, we’re at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting‑edge memory technologies are essential in today’s most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. We’re looking for innovative minds to join our mission of shaping the future of technology. At SK hynix America, you’ll be part of a team that’s pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We’re not just adapting to technological change – we’re driving it, with significant investments in artificial intelligence, machine learning, and eco‑friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what’s possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Job Summary: To strengthen leadership in the DRAM‑on‑Logic era through optimized DRAM die design, we are seeking talent capable of driving the co‑design of 3D‑stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.

Responsibilities

• Strengthen leadership in the DRAM‑on‑Logic Era through advanced digital IP design for 3D-Stacked DRAM.
• Provide digital IP services for 3D-stacked DRAM to enable DRAM‑on‑Logic system configurations for customers.
• Establish close technical engagement with foundry companies to build digital IP of 3D-stacked DRAM.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
• Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
• Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
• Experience with memory controllers.
• Experience in memory Built-in Self-Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
• Deep understanding of PPA analysis and optimization, and physical design.
• Excellent verbal and written communication in English; ability to present technical concepts to cross-functional teams and senior management.

SKHYA is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.

Compensation: Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.

Pay Range: $150,000 - $260,000 USD