Lead 3D Memory Architect & Near-Memory Design

Qualcomm; San Diego (CA); Hybrid; USD 192,000 - 288,000; Full time

Job summary

Qualcomm Technologies, Inc. in California seeks a senior expert to advance 3D memory design and near-memory computing for data center, mobile, compute, and XR workloads. You will optimize memory architectures to maximize bandwidth, latency, and energy efficiency while exploring 3D integration and fabrics.

The role collaborates with process/packaging teams, AI architects, and memory/controller groups to drive architecture trade-offs and cross-organizational alignment.

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design/verification experience.
• Master's degree in Science, Engineering, or related field and 7+ years of ASIC design/verification experience.
• PhD in Science, Engineering, or related field and 6+ years of ASIC design/verification experience.

Responsibilities

• Develop and optimize 3D DRAM/FLASH organization and near-memory computing architectures.
• Develop and validate models for 3D Memory performance, power, and yield.
• Develop novel fabrics for distribution of high-bandwidth data from 3D DRAM to near-memory units.
• Develop memory power distribution topology for robust 3D stack operation.
• Simulate and emulate system performance of 3D memory architectures across workloads.
• Floorplan 3D memory chips and design memory array control structures under 3D constraints.
• Knowledge about chip connection fabrics such as UCIe, UAL, LPDDR, HBM3/4, PCIe

Skills

RTL

SoC architecture

Memory architecture

Verilog-AMS modeling

C/C++

3D memory/near-memory

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

EDA tools

MATLAB

Phyton

Job description

Qualcomm Technologies, Inc. in California seeks a senior expert to advance 3D memory design and near-memory computing for data center, mobile, compute, and XR workloads. You will optimize memory architectures to maximize bandwidth, latency, and energy efficiency while exploring 3D integration and fabrics.

The role collaborates with process/packaging teams, AI architects, and memory/controller groups to drive architecture trade-offs and cross-organizational alignment.