Senior IC Layout Engineer

Insight Global; Irvine (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Insight Global seeks an experienced Analog/RF Layout Engineer to develop custom physical layouts for high-speed analog and mixed-signal designs in Irvine, CA. Translate schematics into DRC/LVS-clean layouts and own IP blocks from floorplanning to tape-out, collaborating with circuit designers on floorplanning, routing, and parasitic optimization.

The role requires strong hands-on Cadence Virtuoso/VXL and Mentor Calibre experience, with a track record on FinFET nodes and device matching.

Qualifications

• BS in Electrical Engineering or related field with 8+ years of experience or MS with 6+ years.
• Extensive analog and high-speed layout experience including TX/RX/SerDes/PLL.
• Hands-on Cadence Virtuoso and Virtuoso VXL for custom IC layout.
• Experience with Mentor Calibre for DRC/LVS verification and sign-off.
• Proven layout experience with advanced FinFET process nodes.
• Strong understanding of device matching, critical-net routing, and power/ground.

Responsibilities

• Translate analog, mixed-signal, and high-speed schematics into production-ready physical layouts.
• Own custom IP and top-level layouts from initial floorplanning through tape-out and sign-off.
• Perform precision device matching and critical-net routing to meet high-frequency performance.
• Collaborate with circuit designers on floorplanning, power/ground architecture, layout strategy, and parasitic optimization.
• Run and resolve DRC/LVS verification using Cadence and Calibre tools.
• Develop layouts on advanced FinFET nodes addressing geometry, routing, and physical-design constraints.
• Support top-level integration, project scheduling, and physical-design readiness for silicon tape-out.

Skills

Analog layout

High-speed layout

Device matching

Parasitics optimization

Cross-functional collaboration

Problem solving

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Cadence Virtuoso

Virtuoso VXL

Mentor Calibre

Job description

Job Description

Job DescriptionWe are seeking an experienced Analog/RF Layout Engineer to develop custom physical layouts for high-speed analog and mixed-signal semiconductor designs. This engineer will translate circuit schematics into DRC/LVS-clean layouts while partnering closely with circuit designers on floorplanning, device matching, critical-net routing, power architecture, and parasitic optimization. The role will own custom IP and top-level blocks from initial floorplanning through verification, integration, and tape-out. The ideal candidate has extensive experience with high-speed circuits such as TX, RX, SerDes, and PLL designs. Strong hands‑on expertise with Cadence Virtuoso, Virtuoso VXL, Mentor Calibre, and advanced FinFET process nodes is required.

Key Responsibilities

• Translate analog, mixed‑signal, and high‑speed circuit schematics into production‑ready physical layouts
• Own custom IP and top‑level layouts from initial floorplanning through final tape‑out and sign‑off
• Perform precision device matching and critical‑net routing to meet high‑frequency circuit performance requirements
• Partner with circuit designers on floorplanning, power/ground architecture, layout strategy, and parasitic optimization
• Run and resolve DRC/LVS verification using Cadence and Calibre tools
• Develop layouts on advanced FinFET technology nodes while addressing complex geometry, routing, and physical‑design constraints
• Support top‑level integration, project scheduling, and physical‑design readiness for silicon tape‑out

Skills and Requirements

Required Skills and Experience:

• BS in Electrical Engineering or related field with 8+ years of experience, or MS with 6+ years of related experience
• Extensive experience with custom analog and high‑speed circuit layout, including TX, RX, SerDes, PLL, or similar IP
• Strong hands‑on experience with Cadence Virtuoso and Virtuoso VXL for custom IC layout
• Experience with Mentor Calibre for DRC/LVS verification and physical sign‑off
• Proven layout experience with advanced FinFET process nodes
• Strong understanding of analog layout fundamentals, including device matching, critical‑net routing, parasitics, and power/ground architecture
• Experience taking custom IP blocks through floorplanning, layout, verification, integration, and tape‑out
• Strong problem‑solving and cross‑functional collaboration skills

Nice to Have Skills and Experience:

• Scripting skills (Tcl, Perl, Python, etc.)
• Previous tape‑out experience

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [e-mail].