Junior AI Silicon SoC Design Engineer

Unconventional, Inc.; Mountain View (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Complimentary meals (Palo Alto)

Job summary

Unconventional, Inc. in Mountain View, CA, seeks a Junior Member of Technical Staff - AI Silicon Digital Design Engineer to drive foundational work on our AI-focused SoC platform. You will contribute to micro-architecture, integrate CPU blocks, and implement high-performance RTL for digital interfaces.

Responsibilities include synthesis, timing, CDC/lint checks, DV support, and coordination with internal teams. Strong Verilog RTL coding skills and 4+ years in ASIC/SoC design are essential.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of industry experience in digital ASIC/SoC design.
• Expertise in Verilog RTL coding and digital design fundamentals.
• Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and CDC analysis.
• Understanding of the full ASIC design flow from specification to tape-out.

Responsibilities

• SoC Design & Integration: contribute to micro-architecture and integration of digital blocks including CPU, interfaces, and memory subsystems.
• Hands-on RTL implementation: write synthesizable Verilog/SystemVerilog code and implement/ debug key digital interfaces to meet PPA targets.
• Synthesis & Timing: perform initial synthesis and timing constraints; lint CDC checks.

Skills

Verilog RTL coding

Digital design fundamentals

Communication skills

Problem solving

Education

B.S. or M.S. in Electrical Engineering or related field

Tools

EDA tools

Job description

Unconventional, Inc. in Mountain View, CA, seeks a Junior Member of Technical Staff - AI Silicon Digital Design Engineer to drive foundational work on our AI-focused SoC platform. You will contribute to micro-architecture, integrate CPU blocks, and implement high-performance RTL for digital interfaces.

Responsibilities include synthesis, timing, CDC/lint checks, DV support, and coordination with internal teams. Strong Verilog RTL coding skills and 4+ years in ASIC/SoC design are essential.