Senior AI Silicon Physical Design Engineer

Unconventional, Inc.; United States; Remote; USD 260,000 - 400,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Complimentary meals

Job summary

Unconventional, Inc. is assembling a foundational R&D team in the United States to deliver a next-generation AI accelerator platform. You will own the end-to-end physical implementation from RTL to GDSII, targeting aggressive PPA goals and first-pass silicon success.

You will work at the intersection of architecture and silicon, collaborating with digital and analog teams and external partners to push the frontiers of energy-efficient hardware for AI. Mountain View office site access is included.

Qualifications

• BS or MS in Electrical/Computer Engineering or related field.
• 10+ years of digital physical design with tapeouts on modern nodes (7nm/5nm+ preferred).
• Expertise in STA and timing closure for high-frequency designs.
• Deep understanding of physical design challenges on advanced nodes and low-voltage operation.
• Proficient in power integrity analysis and noise coupling mitigation.
• Mastery of standard EDA tool suites and scripting to automate flows.

Responsibilities

• Own RTL-to-GDSII flow for complex blocks and SoC integration, including floorplanning, CTS, routing and verification.
• Drive aggressive Power, Performance, and Area targets in collaboration with architects.
• Own sign-off processes: STA, IR drop, EM, DRC/LVS/ERC.
• Develop and automate physical design workflows; implement best practices.
• Collaborate with digital/analog teams and evaluate AI design tooling partnerships.

Skills

STA & timing closure

Physical design for advanced nodes

Power integrity analysis

EDA tool proficiency

Scripting (Tcl, Python, Perl)

Vendor collaboration

Education

B.S. or M.S. in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

Cadence Innovus

IC Compiler II

Job description

Unconventional, Inc. is assembling a foundational R&D team in the United States to deliver a next-generation AI accelerator platform. You will own the end-to-end physical implementation from RTL to GDSII, targeting aggressive PPA goals and first-pass silicon success.

You will work at the intersection of architecture and silicon, collaborating with digital and analog teams and external partners to push the frontiers of energy-efficient hardware for AI. Mountain View office site access is included.