IP Verification Engineer — FPGA/ASIC Frontend

AMD; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD in San Jose is seeking a verification engineer in the AECG Group to help bring to life FPGA and ASIC designs for diverse customers. You will work with front-end design, architecture, IP, PD, and product engineers to achieve first-pass silicon success.

You will develop UVM testbenches, run regressions, and drive feature verification across software, firmware, and hardware interfaces. The role demands strong problem-solving, collaboration across sites/time zones, and a passion for modern IP

Qualifications

• IP verification and testbench development experience.
• Technical leadership across project lifecycle.
• Experience with PCIe, CXL, NVMe or Ethernet protocols.
• Expert in Verilog and SystemVerilog, OO programming.
• Expert in UVM verification frameworks and testbenches.
• Experience applying AI to automate verification processes.
• familiarity with simulation profiles and acceleration tools.
• Strong computer architecture and systems knowledge.
• Proficient in Python or Perl scripting.
• Excellent communication and cross-site collaboration.

Responsibilities

• Collaborate with architects, hardware, firmware and software teams to verify new features.
• Develop test plans accounting for interactions with hardware, firmware and drivers.
• Code IP or SS level UVM based testbenches and monitors.
• Build directed and random verification tests.
• Run regressions and debug failures to ensure high-quality silicon.

Skills

IP verification

Technical leadership

PCIe / CXL / NVMe / Ethernet

Verilog / SystemVerilog

UVM testbenches

AI in verification

HLS tools / acceleration

Computer architecture

Python / Perl scripting

Cross-site collaboration

Education

Bachelors or Masters in computer/electrical engineering

Tools

UVM Framework

Job description

AMD in San Jose is seeking a verification engineer in the AECG Group to help bring to life FPGA and ASIC designs for diverse customers. You will work with front-end design, architecture, IP, PD, and product engineers to achieve first-pass silicon success.

You will develop UVM testbenches, run regressions, and drive feature verification across software, firmware, and hardware interfaces. The role demands strong problem-solving, collaboration across sites/time zones, and a passion for modern IP