Senior Verification Architect – Functional & Performance

AMD; San Jose (CA); On-site; USD 210,000 - 320,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD is seeking a Fellow-level Functional and Performance Verification Architect in San Jose, CA to lead next‑generation pre‑silicon verification strategies within the AECG. You will shape verification architectures, guide cross‑functional teams, and collaborate with EDA partners to enable first‑time‑right silicon.

You will mentor engineers, publish technical papers, and drive scalable methods across IP, subsystem, and SoC programs, ensuring quality, predictability, and on‑time delivery for

Qualifications

• Expert in programming and scripting languages such as C/C++, Python, Perl, and Ruby, along with HDL/Verilog and UVM-based verification.
• Deep background in architecting, developing, and deploying advanced functional verification and validation methodologies, frameworks, and environments for complex semiconductor designs.
• Hands-on experience with pre-silicon prototyping and emulation platforms and their application to functional and performance verification.
• Self-motivated technical leader with a demonstrated ability to identify innovation opportunities, define new methodologies, and drive initiatives from concept through successful deployment.

Responsibilities

• Drive the definition, development, and execution of industry-leading functional and performance verification and validation strategies, encompassing verification planning, testbench architecture, development of verification collaterals, debug methodologies, and coverage closure across IP, subsystem, and SoC programs within AECG and AMD.
• Lead the evolution of simulation-based verification methodologies, encompassing constrained-random, directed, and coverage-driven approaches, while advancing formal, power, performance, and implementation verification strategies across the verification organization.
• Lead the evolution of firmware-based validation strategies and methodologies across prototyping and emulation platforms, accelerating verification convergence and silicon readiness.
• Influence and shape the evolution of verification methodologies by working closely with AECG executives and senior leaders to address the needs of current and future silicon programs.
• Work closely with architecture, design, and verification leaders to identify emerging challenges, align on requirements, and develop scalable verification methodologies that improve quality, efficiency, and predictability across future products.

Skills

C/C++

Python

Verilog

UVM

Leadership

Pre-silicon prototyping

Education

B.S./M.S./Ph.D. in EE/CE/CS

Tools

Synopsys

Cadence

Siemens

Job description

AMD is seeking a Fellow-level Functional and Performance Verification Architect in San Jose, CA to lead next‑generation pre‑silicon verification strategies within the AECG. You will shape verification architectures, guide cross‑functional teams, and collaborate with EDA partners to enable first‑time‑right silicon.

You will mentor engineers, publish technical papers, and drive scalable methods across IP, subsystem, and SoC programs, ensuring quality, predictability, and on‑time delivery for