Director of Physical Design

Oho Group; San Francisco (CA); A distancia; USD 250.000 - 400.000; Jornada completa

Descripción de la vacante

OHO Group (Lithuania) seeks a Director of Physical Design to guide a team from research and concept to first silicon on advanced nodes. This hands‑on leadership role owns block‑level and full‑chip PD, builds a team, and collaborates across digital design and verification.

Remote work with occasional travel is possible; Bay Area applicants are preferred. You will drive timing, power integrity, CTS, routing, and tapeout readiness while coordinating with synthesis, STA, DFT and chip‑level teams.

Formación

• 10+ years of hands‑on ASIC/SoC physical design experience.
• Strong experience with Cadence Innovus and end‑to‑end physical design flows.
• Solid understanding of timing constraints, STA, CTS and timing closure.
• Experience with power integrity, IR drop, electromigration and physical verification.
• Strong Tcl scripting skills; Python or Shell experience is beneficial.
• Experience working on advanced process nodes, ideally 7nm or below.

Responsabilidades

• Own block‑level physical design from floorplanning and placement through CTS, routing and signoff.
• Drive timing, congestion, power and signal integrity optimisation.
• Execute timing closure, ECOs and physical verification, including DRC/LVS.
• Work closely with synthesis, STA, DFT and chip‑level teams to support successful integration.
• Contribute to power integrity analysis, design reviews and tapeout readiness.

Conocimientos

ASIC/SoC physical design

Cadence Innovus

Timing constraints

Power integrity

Tcl scripting

Python

Shell scripting

Herramientas

Cadence Innovus

Descripción del empleo

Director of Physical Design – Stealth Startup – Remote

A very well-backed startup are looking for a Director of Physical Design to guide the team through research and concept to first silicon on advanced nodes. A hands‑on technical leadership position, you will own block‑level and full‑chip physical design, build a team and support colleagues across digital design and verification.

Although applicants based in the Bay Area are preferred, they are willing to consider remote work with occasional travel.

Key Responsibilities

• Own block‑level physical design from floorplanning and placement through CTS, routing and signoff.
• Drive timing, congestion, power and signal integrity optimisation.
• Execute timing closure, ECOs and physical verification, including DRC/LVS.
• Work closely with synthesis, STA, DFT and chip‑level teams to support successful integration.
• Contribute to power integrity analysis, design reviews and tapeout readiness.

Requirements

• 10+ years of hands‑on ASIC/SoC physical design experience.
• Strong experience with Cadence Innovus and end‑to‑end physical design flows.
• Solid understanding of timing constraints, STA, CTS and timing closure.
• Experience with power integrity, IR drop, electromigration and physical verification.
• Strong Tcl scripting skills; Python or Shell experience is beneficial.
• Experience working on advanced process nodes, ideally 7nm or below.