IC Design Engineer

Broadcom Inc.; San Jose (CA); On-site; USD 127,100 - 203,400; Full time

Benefits offered by this job

401(K) with company matching

Employee Stock Purchase Program

Paid holidays

Paid sick leave

Vacation time

Job summary

Broadcom Inc. is seeking a skilled engineer to join their Mixed-Signal ASIC Implementation team. The role focuses on developing technologies for consumer devices and satellites. Key responsibilities include leading chip implementation across various technology nodes, from floorplanning to verification.

The ideal candidate will have significant experience with tools like Cadence Innovus and scripting in TCL. Competitive benefits include medical, dental, and retirement plans, alongside an annual bonus and equity awards.

Qualifications

• B.S. in Electrical Engineering with 12+ years or M.S. in Electrical Engineering with 10+ years of experience.
• Experience with multiple tape‑outs and hands‑on knowledge of relevant tools.
• Proficient in using Cadence Innovus; scripting in TCL is a must.

Responsibilities

• Lead and implement chips for high-volume consumer devices.
• Perform physical implementation of blocks and top-level designs.
• Collaborate with internal and external teams for development.

Skills

Cadence Innovus

TCL scripting

Power management

Timing closure

Physical design

Education

B.S. in Electrical Engineering

M.S. in Electrical Engineering

Tools

Innovus

Calibre

VCLP

Formality

Job description

Job Overview

As a member of the Mixed‑Signal ASIC Implementation team, you will participate in developing new technologies for ultra‑low‑power consumer devices and high‑performance satellite projects. Your work will cover the full design flow from physical implementation to timing closure across a range of technology nodes from 40nm to 7nm.

Responsibilities

• Lead and implement chips for high‑volume consumer devices and satellite projects across 40nm, 16nm, and 7nm nodes
• Perform physical implementation of blocks and top‑level designs
• Conduct floorplanning, including multi‑power domain, power‑grid planning, block shaping, and clock‑tree implementation
• Interface with internal and external teams (Design, IP, Library) to coordinate development efforts
• Execute physical verification for block and chip‑level static and dynamic IR drop analysis
• Perform signal and power electromagnetic checks
• Develop methodology and flow for physical design and timing closure
• Collaborate independently with Synthesis and STA owners and RTL design teams to meet physical implementation and power‑intent requirements
• Apply knowledge of ESD, IO padring, analog integration, and package technologies such as flip‑chip and WLCSP
• Leverage AI tools when available

Qualifications

• B.S. in Electrical Engineering with 12+ years of experience or M.S. in Electrical Engineering with 10+ years of experience
• Experience with multiple tape‑outs and hands‑on knowledge of tools such as Innovus, VCLP, Formality, LEC, timing closure, and Calibre
• Proficient use of Cadence Innovus is essential
• Experience scripting in TCL; knowledge of Python is a plus

Compensation & Benefits

Annual base salary range: $127,100 – $203,400. The role is eligible for a discretionary annual bonus and equity awards in accordance with the company’s equity plan.

Benefits include medical, dental, vision, 401(K) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), paid holidays, paid sick leave, vacation time, and compliance with Paid Family Leave and other applicable leaves of absence.

Equal Opportunity

Broadcom is an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, nationality, citizenship, disability status, or any other characteristic protected by law. We also consider qualified applicants with arrest and conviction records in accordance with local law.