Hybrid VLSI ASIC Logic Design Engineer

Anysilicon; Frisco (TX); Hybrid; USD 110,000 - 150,000; Full time

Job summary

Hewlett Packard Enterprise (HPE) is seeking a VLSI ASIC Logic Design Engineer for a hybrid role requiring in-office presence about two days per week. The role involves developing VLSI prototypes, creating SVAs, and applying Formal Verification to ensure design correctness.

You will analyze latency and bandwidth trade-offs and collaborate across teams to resolve issues. The candidate will mentor junior engineers, write verification documentation, and contribute to the design and firmware

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
• 1–6 years of experience in VLSI design, verification, or implementation.

Responsibilities

• Participate as an independent member of a project team of VLSI engineers to develop reliable and cost-effective VLSI prototypes and products.
• Create System Verilog Assertions (SVAs) and utilize Formal Verification to ensure design correctness.
• Write coverage to measure stimulus quality and perform coverage analysis to identify verification gaps.
• Develop documentation to communicate design intent for verification and firmware teams.
• Analyze system latency and bandwidth trade-offs, identifying bottlenecks and proposing solutions.
• Collaborate with management and internal partners on design status, project progress, and issue resolution.
• Mentor less experienced staff in VLSI design and development best practices.

Skills

VLSI principles

Digital logic

Computer architecture

Analytical skills

Communication skills

Education

Bachelor's/Master's in EE/CE

Tools

SystemVerilog

EDA tools

FPGA tools

Job description

Hewlett Packard Enterprise (HPE) is seeking a VLSI ASIC Logic Design Engineer for a hybrid role requiring in-office presence about two days per week. The role involves developing VLSI prototypes, creating SVAs, and applying Formal Verification to ensure design correctness.

You will analyze latency and bandwidth trade-offs and collaborate across teams to resolve issues. The candidate will mentor junior engineers, write verification documentation, and contribute to the design and firmware