Hybrid VLSI ASIC Logic Design Engineer

Hewlett Packard Enterprise Company; Fort Collins (CO); Hybrid; USD 115,000 - 218,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a VLSI ASIC Logic Design Engineer in Colorado. This hybrid role requires you to work on average 2 days per week from an HPE office, with responsibilities spanning SystemVerilog-based VLSI/RTL design, verification planning, and collaboration across design and firmware teams.

The role emphasizes creating SVAs, formal verification, coverage analysis, and mentoring staff while delivering reliable VLSI prototypes and products. Strong English skills required.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent
• 1-6 years of experience in VLSI design, verification, or implementation
• Strong knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
• Strong knowledge of a programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools. Coursework in VLSI design or VLSI concepts.
• Strong written and verbal communication skills; mastery in English and local language.
• Subject matter knowledge in major areas of responsibility. Growing breadth of understanding and a depth of specific expertise.

Responsibilities

• Participates as an independent member of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products.
• VLSI / RTL design using System Verilog.
• Create System Verilog Assertions (SVAs) and use Formal Verification to prove design correctness.
• Write coverage to measure stimulus quality and perform coverage analysis to identify verification holes.
• Create documentation collateral to communicate design intent which guides verification and firmware teams to utilize the design features.
• Explore system latency and bandwidth trade-offs. Identify bottlenecks and propose solutions.
• Collaborates and communicates with management and internal partners regarding design status, project progress, and issue resolution.
• Provides guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.
• Participates as an independent member of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products.

Skills

SystemVerilog

VLSI design

Formal Verification

UVM

HDL

Digital logic

Education

Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent

Tools

EDA tools

FPGA tools

Job description

Hewlett Packard Enterprise is seeking a VLSI ASIC Logic Design Engineer in Colorado. This hybrid role requires you to work on average 2 days per week from an HPE office, with responsibilities spanning SystemVerilog-based VLSI/RTL design, verification planning, and collaboration across design and firmware teams.

The role emphasizes creating SVAs, formal verification, coverage analysis, and mentoring staff while delivering reliable VLSI prototypes and products. Strong English skills required.