Hybrid VLSI Physical Design Engineer

Hewlett Packard Enterprise; BLOOMINGTON (MN); Hybrid; USD 115,000 - 218,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a talented engineer to contribute to ASIC/VLSI design across architecture, physical implementation, and verification. The role focuses on timing analysis, constraints, and achieving robust timing closure for complex designs in an edge-to-cloud environment.

The successful candidate will leverage strong fundamentals in digital logic and algorithms, work with industry-standard EDA tools, and collaborate with cross-functional teams.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent.
• 1–6 years of experience in VLSI design, verification, or implementation.

Responsibilities

• Perform static timing analysis for hierarchical designs at partition and full-chip levels.
• Create, validate, and maintain timing constraints and budgets for design and process requirements.
• Drive timing closure for partition-level and full-chip designs including setup, hold, clock, I/O and test timing.
• Analyze timing reports, identify critical paths, and implement fixes to optimize performance, power, and area.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff, often using AI to improve methodologies.

Skills

Static timing analysis

Timing closure

Synthesis & signoff

Formal verification

Programming/scripting

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

Design Compiler

PrimeTime

Formality

Cadence Genus/LEC

Job description

Hewlett Packard Enterprise is seeking a talented engineer to contribute to ASIC/VLSI design across architecture, physical implementation, and verification. The role focuses on timing analysis, constraints, and achieving robust timing closure for complex designs in an edge-to-cloud environment.

The successful candidate will leverage strong fundamentals in digital logic and algorithms, work with industry-standard EDA tools, and collaborate with cross-functional teams.