Hybrid VLSI Logic Design Intern (SystemVerilog)

Hewlett Packard Enterprise Development LP; Fort Collins (CO); Hybrid; USD 48,000 - 56,000; Full time

Benefits offered by this job

Health & Wellbeing

Personal & Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise invites applications for a VLSI Logic Design Intern position in Colorado. This role is Hybrid, requiring you to work two days per week from an HPE office in the Fort Collins area and collaborating with our Cray Slingshot team on cutting-edge design challenges.

You will assist with VLSI/RTL design using System Verilog, create SVAs, and support coverage analysis, scripting (Python/TCL/Perl) to improve design processes, while learning from a world-class engineering

Qualifications

• Working toward a Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering or equivalent.
• Self-driven with a positive, can-do attitude, and detail-oriented.
• Experience with System Verilog for synthesis (ASIC or FPGA).
• Proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience in executive written and verbal communication skills; mastery in English.
• Ability to work with cross functional teams (DV/Arch/Design/FW).

Responsibilities

• Assist with VLSI / RTL design using System Verilog.
• Assist with creating System Verilog Assertions (SVAs) and use Formal Verification to prove design correctness.
• Assist with writing coverage to measure stimulus quality and perform coverage analysis to identify verification holes.
• Assist with creating scripts (Python, TCL, Perl) to improve design processes and efficiency.

Skills

SystemVerilog

Python

TCL

Perl

C/C++

English

Education

Bachelor's or Master's in EE/CE

Tools

UVM

Job description

Hewlett Packard Enterprise invites applications for a VLSI Logic Design Intern position in Colorado. This role is Hybrid, requiring you to work two days per week from an HPE office in the Fort Collins area and collaborating with our Cray Slingshot team on cutting-edge design challenges.

You will assist with VLSI/RTL design using System Verilog, create SVAs, and support coverage analysis, scripting (Python/TCL/Perl) to improve design processes, while learning from a world-class engineering