Hybrid SoC Analog & Mixed-Signal Design Engineer

Intel Corporation; Hillsboro, Northern (OR, KY); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in Hillsboro, Oregon is seeking a SoC Analog & Mixed-Signal Design Engineer to design and optimize analog and mixed-signal circuits in advanced CMOS process nodes. You will contribute across the design lifecycle—from architecture and simulation to verification—delivering robust IP that meets power, performance, area, timing, and yield goals.

Collaborate with architecture, layout, and other teams to ensure reliable silicon solutions and successful product milestones.

Qualifications

• Analog circuit design and verification experience required.
• Experience with power, area, timing, and yield optimization.
• Familiarity with advanced CMOS process nodes and analog IC design.

Responsibilities

• Design, develop, and build analog circuits in advanced CMOS process nodes.
• Create floorplans, extract chip parameters, and simulate analog behavior models.
• Develop and execute test plans to verify designs against specifications.
• Evaluate results, verify functionality, and optimize for power, area, timing, and yield.
• Collaborate with architecture, layout, and cross-functional teams.

Skills

Analog circuit design

Circuit simulation

Power optimization

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Electronics, or related field

Master's degree in the same fields

PhD in the same field

Tools

Cadence Virtuoso/Spectre

SPICE-based simulation

Process node design experience

Job description

Intel Corporation in Hillsboro, Oregon is seeking a SoC Analog & Mixed-Signal Design Engineer to design and optimize analog and mixed-signal circuits in advanced CMOS process nodes. You will contribute across the design lifecycle—from architecture and simulation to verification—delivering robust IP that meets power, performance, area, timing, and yield goals.

Collaborate with architecture, layout, and other teams to ensure reliable silicon solutions and successful product milestones.